Intel X3330 Specification Update - Page 36

Status: For the steppings affected, see the Summary Tables of Changes. AAA65. VM Entry May Use Wrong Address to Access Virtual-APIC Page Problem: When XFEATURE_ENABLED_MASK register (XCR0) bit 1 (SSE) is 1, a VM entry executed with the "use TPR shadow" VM-execution control set to 1 may use the wrong address to access data on the virtual-APIC page. Implication: An affected VM entry may exhibit the following behaviors: (1) it may use wrong areas of the virtual-APIC page to determine whether VM entry fails or whether it induces a VM exit due to the TPR threshold; or (2) it may clear wrong areas of the virtual-APIC page. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AAA66. XRSTORE Instruction May Cause Extra Memory Reads Problem: An XRSTOR instruction will cause non-speculative accesses to XSAVE memory area locations containing the FCW/FSW and FOP/FTW Floating Point (FP) registers even though the 64-bit restore mask specified in the EDX:EAX register pair does not indicate to restore the x87 FPU state. Implication: Page faults, data breakpoint triggers, etc. may occur due to the unexpected nonspeculative accesses to these memory locations. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AAA67. CPUID Instruction May Return Incorrect Brand String Problem: When a CPUID instruction is executed with EAX = 8000_0002H, 8000_0003H, or 8000_0004H, the returned EAX, EBX, ECX, and/or EDX values may be incorrect. Implication: When this erratum occurs, the processor may report an incorrect brand string. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AAA68. Global Instruction TLB Entries May Not be Invalidated on a VM Exit or VM Entry Problem: If a VMM is using global page entries (CR4.PGE is enabled and any present pagedirectories or page-table entries are marked global), then on a VM entry, the instruction TLB (Translation Lookaside Buffer) entries caching global page translations of the VMM may not be invalidated. In addition, if a guest is using global page entries, then on a VM exit, the instruction TLB entries caching global page translations of the guest may not be invalidated. Implication: Stale global instruction linear to physical page translations may be used by a VMM after a VM exit or a guest after a VM entry. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AAA69. Problem: When Intel® Deep Power-Down State is Being Used, IA32_FIXED_CTR2 May Return Incorrect Cycle Counts When the processor is operating at an N/2 core to front side bus ratio, after exiting Deep Power-Down State, the internal increment value for IA32_FIXED_CTR2 (Fixed Function Performance Counter 2, 30BH) will not take into account the half ratio setting. 36 Intel® Xeon® Processor 3300 Series Specification Update January 2012