Intel X5472 Specification Update - Page 13

Errata Intel® Xeon® Processor 5400 Series (Sheet 3 of 3) Number Stepping Stepping C-0 E-0 Status (Hardware Fix?) ERRATA AX51 X X No Fix LER MSRs May be Incorrectly Updated AX52 X X No Fix Short Nested Loops That Span Multiple 16-Byte Boundaries May Cause a Machine Check Exception or a System Hang AX53 X X No Fix IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error Reporting Enable Correctly AX54 X An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV X No Fix SS/POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception AX55 X X No Fix A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS AX56 X X No Fix A VM Exit Occurring in IA-32e Mode May Not Produce a VMX Abort When Expected AX57 X X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception AX58 X AX59 AX60 AX61 X No Fix VM Entry May Fail When Attempting to Set IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN X No Fix VM Entry May Use Wrong Address to Access Virtual-APIC Page X No Fix INIT Incorrectly Resets IA32_LSTAR MSR X No Fix CPUID Instruction May Return Incorrect Brand String AX62 X AX63 X No Fix Global Instruction TLB Entries May Not be Invalidated on a VM Exit or VM Entry X No Fix XRSTOR Instruction May Cause Extra Memory Reads AX64 X No Fix Enabling PECI via the PECI_CTL MSR Does Not Enable PECI and May Corrupt the CPUID Feature Flags AX65 X X No Fix Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode AX66 X AX67 X No Fix LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode X No Fix The XRSTOR Instruction May Fail to Cause a General-Protection Exception AX68 AX69 AX70 X AX71 X X No Fix The XSAVE Instruction May Erroneously Modify Reserved Bits in the XSTATE_BV Field X No Fix Store Ordering Violation When Using XSAVE X No Fix Memory Ordering Violation With Stores/Loads Crossing a Cacheline Boundary X No Fix B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set AX72 X X Plan Fix Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction Execution Results AX73 X AX74 X AX75 X AX76 X X No Fix A Page Fault May Not be Generated When the PS bit is set to "1" in a PML4E or PDPTE X No Fix Not-Present Page Faults May Set the RSVD Flag in the Error Code X No Fix VM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction X No Fix A 64-bit Register IP-relative Instruction May Return Unexpected Results 13 Intel® Xeon® Processor 5400 Series Specification Update