MSI P43 User Guide - Page 24

tO ENAblE ThIs ITEm TO rEAD ThE CPu pOwEr cONsUmpTION whIlE IDlE. nOT All prOcEs

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attempts to insert code in the buffer, the processor disables code execution, preventing damage or worm propagation. Set Limit CPUID MaxVal to 3 The Max CPUID Value Limit is designed limit the listed speed of the processor to older operating systems. Intel Virtualization Tech This item is used to enable/disable the Intel Virtualization technology. For further information please refer to Intel's official website. Intel EIST The Enhanced Intel SpeedStep technology allows you to set the performance level of the microprocessor whether the computer is running on battery or AC power. This field will appear after you installed the CPU which support speedstep technology. C1E Support To enable this item to read the CPU power consumption while idle. Not all processors support Enhanced Halt state (C1E ). Adjusted CPU Frequency (MHz) It shows the adjusted CPU frequency (FSB x Ratio). Read-only. MEMORY-Z Press to enter the sub-menu. DIMM1~2 Memory SPD Information Press to enter the sub-menu. The sub-menu displays the information of installed memory. Advance DRAM Configuration Press to enter the sub-menu. DRAM Timing Mode Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect) EEPROM on the DRAM module. Setting to [Auto] enables DRAM timings and the following related items to be determined by BIOS based on the configurations on the SPD. Selecting [Manual] allows users to configure the DRAM timings and the following related items manually. CAS Latency (CL) When the DRAM Timing Mode sets to [Manual], the field is adjustable. This controls the CAS latency, which determines the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. tRCD When the DRAM Timing Mode sets to [Manual], the field is adjustable. When DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. 24

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24
ATTEmpTs TO INsErT cODE IN ThE bUffEr, ThE prOcEssOr DIsAblEs cODE ExEcUTION,
prEvENTINg DAmAgE Or wOrm prOpAgATION.
SET LImIT CPuid MAxVAl TO ²
thE MAx CPuid VAlUE LImIT Is DEsIgNED lImIT ThE lIsTED spEED Of ThE prOcEssOr
TO OlDEr OpErATINg sYsTEms.
iNTEl VIrTUAlIzATION tEch
thIs ITEm Is UsED TO ENAblE/DIsAblE ThE iNTEl VIrTUAlIzATION TEchNOlOgY. FOr fUr-
ThEr INfOrmATION plEAsE rEfEr TO iNTEl’s OfficIAl wEbsITE.
iNTEl eiSt
thE eNhANcED iNTEl SpEEDSTEp TEchNOlOgY AllOws YOU TO sET ThE pErfOrmANcE
lEvEl Of ThE mIcrOprOcEssOr whEThEr ThE cOmpUTEr Is rUNNINg ON bATTErY Or aC
pOwEr. thIs fiElD wIll AppEAr AfTEr YOU INsTAllED ThE CPu whIch sUppOrT spEEDsTEp
TEchNOlOgY.
C±e SUppOrT
tO ENAblE ThIs ITEm TO rEAD ThE CPu pOwEr cONsUmpTION whIlE IDlE. nOT All prOcEs-
sOrs sUppOrT eNhANcED HAlT sTATE (C±e ).
aDjUsTED CPu FrEQUENcY (MHz)
iT shOws ThE ADjUsTED CPu frEQUENcY (FSB x RATIO). READ-ONlY.
MeMoRy-Z
PrEss <eNTEr> TO ENTEr ThE sUb-mENU.
diMM±~2 MEmOrY SPd iNfOrmATION
PrEss <eNTEr> TO ENTEr ThE sUb-mENU. thE sUb-mENU DIsplAYs ThE INfOrmATION
Of INsTAllED mEmOrY.
aDvANcE dRaM CONfigUrATION
PrEss <eNTEr> TO ENTEr ThE sUb-mENU.
dRaM tImINg MODE
SElEcTs whEThEr dRaM TImINg Is cONTrOllED bY ThE SPd (SErIAl PrEsENcE dE-
TEcT) eePRoM ON ThE dRaM mODUlE. SETTINg TO [aUTO] ENAblEs dRaM TImINgs
AND ThE fOllOwINg rElATED ITEms TO bE DETErmINED bY BioS bAsED ON ThE cON-
figUrATIONs ON ThE SPd. SElEcTINg [MANUAl] AllOws UsErs TO cONfigUrE ThE dRaM
TImINgs AND ThE fOllOwINg rElATED ITEms mANUAllY.
CaS LATENcY (CL)
WhEN ThE dRaM tImINg MODE sETs TO [MANUAl], ThE fiElD Is ADjUsTAblE. thIs
cONTrOls ThE CaS lATENcY, whIch DETErmINEs ThE TImINg DElAY (IN clOck cYclEs)
bEfOrE SdRaM sTArTs A rEAD cOmmAND AfTEr rEcEIvINg IT.
TRCd
WhEN ThE dRaM tImINg MODE sETs TO [MANUAl], ThE fiElD Is ADjUsTAblE. WhEN
dRaM Is rEfrEshED, bOTh rOws AND cOlUmNs ArE ADDrEssED sEpArATElY. thIs
sETUp ITEm AllOws YOU TO DETErmINE ThE TImINg Of ThE TrANsITION frOm RaS (rOw
ADDrEss sTrObE) TO CaS (cOlUmN ADDrEss sTrObE). thE lEss ThE clOck cYclEs, ThE
fAsTEr ThE dRaM pErfOrmANcE.