MSI P7NGM DIGITAL User Guide - Page 57

Auto Disable DRAM/PCI Frequency

Page 57 highlights

BIOS Setup tRC W hen the DRAM Timing M ode sets to [Manual], the field is adjustable. The rowcycle time determines the minimum number of clock cycles a memory row takesto complete a full cycle, from row activation up to the precharging of the ac t i ver ow . tWR When the DRAM Timing Mode sets to [Manual], the field is adjustable. Minimum time interval between end of write data burst and the start of a precharge command. Allows sense amplifiers to restore data to cells. tRRD W hen the DRAM Timing Mode sets to [Manual], the field is adjustable. Specifies the active-to-active delay of different banks. Time interval between a read and a precharge command. tWTR When the DRAM Timing Mode sets to [Manual], the field is adjustable. Minimum time interval between the end of write data burst and the start of a column-read command. It allows I/O gating to overdrive sense amplifiers before read command starts. 1T/2T Memory Timing This item controls the SDRAM command rate. Select [1T] makes SDRAM signal controller to run at 1T (T=clock cycles) rate. Selecting [2T] makes SDRAM signal controller run at 2T rate. Adjust Memory Clock (M Hz) This item allows you to set the Memory frequency (in MHz). This item will disappear after you set System Clock Mode to [Unlinked]. FSB/DRAM Ratio This item will allow you to adjust the ratio of FSB to memory. This item will disappear after you set System Clock Mode to [Linked]. Adjusted DRAM Frequency (MHz) It shows the adjusted memory frequency. Read-only. Adjust PCI-E Frequency (MHz) This field allows you to select the PCI-E frequency (in MHz). Auto Disable DRAM /PCI Frequency W hen set to [Enabled], the system will remove (turn off) clocks from empty DIMM and PCI slots to minimize the electromagnetic interference (EMI). CPU Voltage (V) This item allows you to increase the CPU voltage. 3-21

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3-21
BIOS Setup
tRC
When the
DRAM Timing Mode
sets to [Manual], the field is adjustable. The
rowcycle time determines the minimum number of clock cycles a memory row
takesto complete a full cycle, from row activation up to the precharging of the
activerow.
tWR
When the
DRAM Timing Mode
sets to [Manual], the field is adjustable. Minimum
time interval between end of write data burst and the start of a precharge
command. Allows sense amplifiers to restore data to cells.
tRRD
When the
DRAM Timing Mode
sets to [Manual], the field is adjustable. Speci-
fies the active-to-active delay of different banks. Time interval between a read
and a precharge command.
tWTR
When the
DRAM Timing Mode
sets to [Manual], the field is adjustable. Minimum
time interval between the end of write data burst and the start of a column-read
command. It allows I/O gating to overdrive sense amplifiers before read com-
mand starts.
1T/2T Memory Timing
This item controls the SDRAM command rate. Select [1T] makes SDRAM signal
controller to run at 1T (T=clock cycles) rate. Selecting [2T] makes SDRAM signal
controller run at 2T rate.
Adjust Memory Clock (MHz)
This item allows you to set the Memory frequency (in MHz). This item will disappear
after you set
System Clock Mode
to [Unlinked].
FSB/DRAM Ratio
This item will allow you to adjust the ratio of FSB to memory. This item will disappear
after you set
System Clock Mode
to [Linked].
Adjusted DRAM Frequency (MHz)
It shows the adjusted memory frequency. Read-only.
Adjust PCI-E Frequency (MHz)
This field allows you to select the PCI-E frequency (in MHz).
Auto Disable DRAM/PCI Frequency
When set to [Enabled], the system will remove (turn off) clocks from empty DIMM and
PCI slots to minimize the electromagnetic interference (EMI).
CPU Voltage (V)
This item allows you to increase the CPU voltage.