Seagate ST34321A Product Manual - Page 30

22 Medalist 8641, 6531, 4321, 3221 and 2110, Rev. B Drive pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal name Reset- Ground DD7 DD8 DD6 DD9 DD5 DD10 DD4 DD11 DD3 DD12 DD2 DD13 DD1 DD14 DD0 DD15 Ground (removed) DMARQ Ground DIOW-: STOP Ground DIOR-: HDMARDY-: HSTROBE Ground IORDY: DDMARDY-: DSTROBE CSEL DMACK- Ground INTRQ IOCS16- DA1 PDIAG- DA0 DA2 CS0- CS1- DASP- Ground Host pin # and signal description 1 Hardware Reset 2 Ground 3 Host Data Bus Bit 7 4 Host Data Bus Bit 8 5 Host Data Bus Bit 6 6 Host Data Bus Bit 9 7 Host Data Bus Bit 5 8 Host Data Bus Bit 10 9 Host Data Bus Bit 4 10 Host Data Bus Bit 11 11 Host Data Bus Bit 3 12 Host Data Bus Bit 12 13 Host Data Bus Bit 2 14 Host Data Bus Bit 13 15 Host Data Bus Bit 1 16 Host Data Bus Bit 14 17 Host Data Bus Bit 0 18 Device Data (15:0) 19 Ground 20 (No Pin) 21 DMA Request 22 Ground 23 Device I/O Write: Stop Ultra DMA Burst 24 Ground 25 Device I/O Read: Host Ultra DMA Ready: Host Ultra DMA Data Strobe 26 Ground 27 I/O Channel Ready Device Ultra DMA Ready Device Ulta DMA Data Strobe 28 Cable Select 29 DMA Acknowledge 30 Ground 31 Device Interrupt 32 Reserved 33 Host Address Bus Bit 1 34 Passed Diagnostics 35 Device Address (2:0) 36 Device Address (2:0) 37 Chip Select (1:0) 38 Chip Select (1:0) 39 Drive Active / Slave Present 40 Ground Pins 28, 34 and 39 are used for master-slave communication (details shown below). Drive 1 (slave) 28 34 39 Drive 0 (master) 28 34 39 CSEL PDIAG- DASP- Host 28 34 39 Figure 4. I/O pins and supported ATA signals