AMD OS1354WBJ4BGHBOX Optimization Guide - Page 11

the

two

integer

ALU

pipes

,

the

load

address

generation

pipe

,

the

store

address

generation

pipe

,

and

the

two

FPU

pipes

.

A

macro-op

is

eligible

to

be

committed

by

the

retire

unit

when

all

corresponding

micro-ops

have

finished

execution

.

The

retire

unit

handles

in-order

commit

of

up

to

two

macro-ops

per

cycle

.

2.4

Processor

Block

Diagram

A

block

diagram

of

the

AMD

Family

16

h

processor

is

shown

below

.

Figure

1.

Family

16

h

Processor

Block

Diagram

2.5

Processor

Cache

Operations

AMD

Family

16

h

processors

use

three

different

caches

to

accelerate

instruction

execution

and

data

processing

:

•

Dedicated

L

1

instruction

cache

•

Dedicated

L

1

data

cache

•

Unified

L

2

cache

shared

by

up

to

four

cores

52128

Rev

. 1.1

March

2013

Software

Optimization

Guide

for

AMD

Family

16

h

Processors

Chapter

2

Microarchitecture

of

the

Family

16

h

Processor

11

Section	Page
Contents	3
List of Figures	4
List of Tables	5
Revision History	6
1 Preface	7
2 Microarchitecture of the Family 16h Processor	8
2.1 Features	8
2.2 Instruction Decomposition	10
2.3 Superscalar Organization	10
2.4 Processor Block Diagram	11
2.5 Processor Cache Operations	11
2.5.1 L1 Instruction Cache	12
2.5.2 L1 Data Cache	12
2.5.3 L2 Cache	12
2.6 Memory Address Translation	13
2.6.1 L1 Translation Lookaside Buffers	13
2.6.2 L2 Translation Lookaside Buffers	13
2.6.3 Hardware Page Table Walker	13
2.7 Optimizing Branching	13
2.7.1 Branch Prediction	13
2.7.1.1 Next Address Logic	14
2.7.1.2 Branch Target Buffer	14
2.7.1.3 Branch Target Address Calculator	14
2.7.1.4 Out-of-Page Target Array	15
2.7.1.5 Branch Marker Caching	15
2.7.1.6 Return Address Stack	15
2.7.1.7 Indirect Target Predictor	16
2.7.1.8 Conditional Branch Predictor	16
2.7.1.9 Fetch Window Tracking Structure	16
2.7.2 Loop Alignment	16
2.7.2.1 Encoding Padding for Loop Alignment	16
2.7.2.2 Aligning Loops to Reduce Power Consumption	17
2.8 Instruction Fetch and Decode	18
2.9 Integer Unit	18
2.9.1 Integer Schedulers	18
2.9.2 Integer Execution Units	18
2.9.3 Retire Control Unit	19
2.10 Floating-Point Unit	19
2.10.1 Denormals	21
2.11 XMM Register Merge Optimization	22
2.12 Load Store Unit	23
Appendix A Instruction Latencies	24
A.1 Instruction Latency Assumptions	24

AMD OS1354WBJ4BGHBOX Optimization Guide - Page 11

Processor, Block, Diagram, Cache, Operations

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