AMD OS1354WBJ4BGHBOX Optimization Guide - Page 8

Microarchitecture, Family, Processor

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Software Optimization Guide for AMD Family 16h Processors 52128 Rev. 1.1 March 2013 2 Microarchitecture of the Family 16h Processor An understanding of the terms architecture, microarchitecture, and design implementation is important when discussing processor design. The architecture consists of the instruction set and those features of a processor that are visible to software programs running on the processor. The architecture determines what software the processor can run. The AMD64 architecture of the AMD Family 16h processor is compatible with the industry-standard x86 instruction set. The term microarchitecture refers to the design features used to reach the cost, performance, and functionality goals of the processor. The design implementation refers to a particular combination of physical logic and circuit elements that comprise a processor that meets the microarchitecture specifications. The AMD Family 16h processor employs a reduced instruction set execution core with a preprocessor that decodes and decomposes most of the simpler AMD64 instructions into a sequence of one or two macro-ops. More complex instructions are implemented using microcode routines. Decode is decoupled from execution and the execution core employs a super-scalar organization in which multiple execution units operate essentially independently. The design of the execution core allows it to implement a small number of simple instructions which can be executed in a single processor cycle. This design simplifies circuit design, achieving lower power consumption and fast execution at optimized processor clock frequencies. This chapter covers the following topics: Topic Features Instruction Decomposition Superscalar Organization Processor Block Diagram Processor Cache Operations Memory Address Translation Optimizing Branching Instruction Fetch and Decode Integer Unit Floating-Point Unit XMM Register Merge Optimization Load Store Unit 2.1 Features This topic introduces some of the key features of the AMD Family 16h Processor. The AMD Family 16h processor implements a specific subset of the AMD64 instruction set architecture. Instruction set architecture support includes: • General-purpose instructions, including support for 64-bit operands • x87 Floating-point instructions • 64-bit Multi-media (MMX) instructions 8 Microarchitecture of the Family 16h Processor Chapter 2

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2
Microarchitecture
of
the
Family
16
h
Processor
An
understanding
of
the
terms
architecture
,
microarchitecture
,
and
design
implementation
is
important
when
discussing
processor
design
.
The
architecture
consists
of
the
instruction
set
and
those
features
of
a
processor
that
are
visible
to
software
programs
running
on
the
processor
.
The
architecture
determines
what
software
the
processor
can
run
.
The
AMD
64
architecture
of
the
AMD
Family
16
h
processor
is
compatible
with
the
industry-standard
x
86
instruction
set
.
The
term
microarchitecture
refers
to
the
design
features
used
to
reach
the
cost
,
performance
,
and
functionality
goals
of
the
processor
.
The
design
implementation
refers
to
a
particular
combination
of
physical
logic
and
circuit
elements
that
comprise
a
processor
that
meets
the
microarchitecture
specifications
.
The
AMD
Family
16
h
processor
employs
a
reduced
instruction
set
execution
core
with
a
preprocessor
that
decodes
and
decomposes
most
of
the
simpler
AMD
64
instructions
into
a
sequence
of
one
or
two
macro-ops
.
More
complex
instructions
are
implemented
using
microcode
routines
.
Decode
is
decoupled
from
execution
and
the
execution
core
employs
a
super-scalar
organization
in
which
multiple
execution
units
operate
essentially
independently
.
The
design
of
the
execution
core
allows
it
to
implement
a
small
number
of
simple
instructions
which
can
be
executed
in
a
single
processor
cycle
.
This
design
simplifies
circuit
design
,
achieving
lower
power
consumption
and
fast
execution
at
optimized
processor
clock
frequencies
.
This
chapter
covers
the
following
topics
:
Topic
Features
Instruction
Decomposition
Superscalar
Organization
Processor
Block
Diagram
Processor
Cache
Operations
Memory
Address
Translation
Optimizing
Branching
Instruction
Fetch
and
Decode
Integer
Unit
Floating-Point
Unit
XMM
Register
Merge
Optimization
Load
Store
Unit
2.1
Features
This
topic
introduces
some
of
the
key
features
of
the
AMD
Family
16
h
Processor
.
The
AMD
Family
16
h
processor
implements
a
specific
subset
of
the
AMD
64
instruction
set
architecture
.
Instruction
set
architecture
support
includes
:
•
General-purpose
instructions
,
including
support
for
64
-bit
operands
•
x
87
Floating-point
instructions
•
64
-bit
Multi-media
(
MMX
instructions
Software
Optimization
Guide
for
AMD
Family
16
h
Processors
52128
Rev
. 1.1
March
2013
8
Microarchitecture
of
the
Family
16
h
Processor
Chapter
2