ASRock A620M-HDV/M.2 Software/BIOS Setup Guide - Page 37
Dram ODT impedance RTT_NOM_WR
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AMD X670/B650 Series Twrrd The minimum number of cycles from the last clock of virtual CAS of the first writeburst operation to the clock in which CAS is asserted for a following read-burst operation. Trdwr The minimum number of cycles from the last clock of virtual CAS of the first readburst operation to the clock in which CAS is asserted for a following write-burst operation. DRAM Bus Control Configuration Press [Enter] to configure DRAM Bus Control options. Power Down Enable Allows you to enable or disable DDR5 power down mode. Configuration options: [Auto] [Disabled] [Enabled] Dram ODT impedance RTT_NOM_RD Allows you to specify the Dram ODT impedance RTT_NOM_RD. Configuration options: [Auto] [RTT_OFF] [RZQ (240)] [RZQ/2 (120)] [RZQ/3 (80)] [RZQ/6 (60)] [RZQ/5 (48)] [RZQ/6 (40)] [RZQ/7 (34)] Dram ODT impedance RTT_NOM_WR Allows you to specify the Dram ODT impedance RTT_NOM_WR. Configuration options: [Auto] [RTT_OFF] [RZQ (240)] [RZQ/2 (120)] [RZQ/3 (80)] [RZQ/6 (60)] [RZQ/5 (48)] [RZQ/6 (40)] [RZQ/7 (34)] Dram ODT impedance RTT_WR Allows you to specify the Dram ODT impedance RTT_WR. Configuration options: [Auto] [RTT_OFF] [RZQ (240)] [RZQ/2 (120)] [RZQ/3 (80)] [RZQ/6 (60)] [RZQ/5 (48)] [RZQ/6 (40)] [RZQ/7 (34)] Dram ODT impedance RTT_PARK Allows you to specify the Dram ODT impedance RTT_PARK. Configuration options: [Auto] [RTT_OFF] [RZQ (240)] [RZQ/2 (120)] [RZQ/3 (80)] [RZQ/6 (60)] [RZQ/5 (48)] [RZQ/6 (40)] [RZQ/7 (34)] Dram ODT impedance DQS_RTT_PARK Allows you to specify the Dram ODT impedance DQS_RTT_PARK. Configuration options: [Auto] [RTT_OFF] [RZQ (240)] [RZQ/2 (120)] [RZQ/3 (80)] 33