ASRock H170M Pro4S User Manual - Page 54

Four Activate Window tFAW

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H170M Pro4S Read to Precharge (tRTP) he number of clocks that are inserted between a read command to a row precharge command to the same rank. Four Activate Window (tFAW) he time window in which four activates are allowed the same rank. CAS Write Latency (tCWL) Conigure CAS Write Latency. Third Timing tREFI Conigure refresh cycles at an average periodic interval. tCKE Conigure the period of time the DDR4 initiates a minimum of one refresh command internally once it enters Self-Refresh mode. tRDRD_sg Conigure between module read to read delay. tRDRD_dg Conigure between module read to read delay. tRDRD_dr Conigure between module read to read delay. tRDRD_dd Conigure between module read to read delay. tRDWR_sg Conigure between module read to write delay. tRDWR_dg Conigure between module read to write delay. tRDWR_dr Conigure between module read to write delay. 49 English

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49
English
H170M Pro4S
Read to Precharge (tRTP)
He number of clocks that are inserted between a read command to a row pre-
charge command to the same rank.
Four Activate Window (tFAW)
He time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Con±gure CAS Write Latency.
Third Timing
tREFI
Con±gure refresh cycles at an average periodic interval.
tCKE
Con±gure the period of time the DDR4 initiates a minimum of one refresh
command internally once it enters Self-Refresh mode.
tRDRD_sg
Con±gure between module read to read delay.
tRDRD_dg
Con±gure between module read to read delay.
tRDRD_dr
Con±gure between module read to read delay.
tRDRD_dd
Con±gure between module read to read delay.
tRDWR_sg
Con±gure between module read to write delay.
tRDWR_dg
Con±gure between module read to write delay.
tRDWR_dr
Con±gure between module read to write delay.