ASRock H170M Pro4S User Manual - Page 55

tRDWR_dd, tWRRD_sg, tWRRD_dg, tWRRD_dr, tWRRD_dd, tWRWR_sg, tWRWR_dg, tWRWR_dr, tWRWR_dd, RTL CH A,

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Page 55 highlights

tRDWR_dd Conigure between module read to write delay. tWRRD_sg Conigure between module write to read delay. tWRRD_dg Conigure between module write to read delay. tWRRD_dr Conigure between module write to read delay. tWRRD_dd Conigure between module write to read delay. tWRWR_sg Conigure between module write to write delay. tWRWR_dg Conigure between module write to write delay. tWRWR_dr Conigure between module write to write delay. tWRWR_dd Conigure between module write to write delay. RTL (CH A) Conigure round trip latency for channel A. RTL (CH B) Conigure round trip latency for channel B. IO-L (CH A) Conigure IO latency for channel A. IO-L (CH B) Conigure IO latency for channel B. 50 English

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50
English
tRDWR_dd
Con±gure between module read to write delay.
tWRRD_sg
Con±gure between module write to read delay.
tWRRD_dg
Con±gure between module write to read delay.
tWRRD_dr
Con±gure between module write to read delay.
tWRRD_dd
Con±gure between module write to read delay.
tWRWR_sg
Con±gure between module write to write delay.
tWRWR_dg
Con±gure between module write to write delay.
tWRWR_dr
Con±gure between module write to write delay.
tWRWR_dd
Con±gure between module write to write delay.
RTL (CH A)
Con±gure round trip latency for channel A.
RTL (CH B)
Con±gure round trip latency for channel B.
IO-L (CH A)
Con±gure IO latency for channel A.
IO-L (CH B)
Con±gure IO latency for channel B.