Acer AL2423W AL2423W LCD Monitor - Page 51

5 4 3 +1.8_DVDD +1.8V_AVDD FB1 L1206 FB3 L1206 C67 47uF/10V C68 C6C969 0.1uF 0.10u.1FuF C70 0.1uF C71 0.1uF C72 0.1uF C49 47uF/10V C50 0.1uF C51 0.1uF C52 0.1uF C53 0.1uF C54 0.1uF C55 0.1uF C56 0.1uF +3.3_AVDD +3.3_ADCV FB5 L1206 GND GND +3.3_AVDD FB6 L1206 3.3V_AVDD U7 C81 C82 C83 C84 C85 C86 C87 C88 47uF/10V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 22uF/10V D +5V GND C89 22uF/10V C90 0.1uF GND R81 CN3 10K 1 UART_DO/BOOT3 2 UART_DI 3 4 AMP 640456-4 gProbe GND +5V UART_D0_IN 3 Q15 22N7002E R88 6K Connect SDA to UART_DO, SCL to UART_DI 10/14/2005 3.3V_AVDD C96 22pF X1 C97 22pF 14.318MHz DDC_SCL_DVI DDC_SDA_DVI DDC_SCL_VGA DDC_SDA_VGA DDC_SCL_0 DDC_SDA_0 XTAL TCLK R228 4.7K 1 R229 2.7K RESETn Modify I2C 5/3V switch 11/2 +3.3_DVDD C R95 10K R97 10K R92 13.5K C100 0.01uF GND GND GPIO_9/PW M3/BOOT7 GPIO_8/PW M2/BOOT6 BOOTSTRAP Lo Int ROM selects Lo TCLK 14.318MHz GPIO9 PWM0 Lo Int ROM selects Hi TCLK 20MHz Hi Int ROM selects Lo TCLK 24MHz Hi Int ROM selects Hi TCLK 19.661MHz HSYNC2 VSYNC2 HSYNC1 VSYNC1 BLUE2+ SOGMCSS2 GREEN2+ RED2+ R96 85R 1% R98 85R 1% R99 85R 1% C101 0.1uF C102 R104 10K/NC R105 PWM0/BOOT5 10K GPIO8 Lo Standard SPI i/f Hi Atmel Data Flash 1/f GND BLUE1+ SOGMCSS1 GREEN1+ RED1+ 0.1uF C103 107 115 123 158 160 164 140 151 154 111 119 130 131 124 125 128 129 191 192 162 163 165 132 133 136 137 139 141 142 144 146 147 0.1uF 148 150 152 153 155 VDD_DVI_1.8 VDD_DVI_1.8 VDD_DVI_1.8 VDD1_ADC_1.8 VDD_RPLL_1.8 AVDD_RPLL_3.3 VDDA_ADC_3.3 VDDA_ADC_3.3 VDDA_ADC_3.3 VDDA_DVI_3.3 VDDA_DVI_3.3 UART_DI UART_DO/BOOT[3] DDC_SCL_CH2 DDC_SDA_CH2 DDC_SCL_CH1 DDC_SDA_CH1 GPIO_0/DDC_SCL_0 GPIO_1/DDC_SDA_0 XTAL TCLK RESETn HSYNC2 VSYNC2 HSYNC1 VSYNC1 BLUE2+ SOG_MCSS2 GREEN2+ RED2+ BLUEGREENRED- BLUE1+ SOG_MCSS1 GREEN1+ RED1+ R108 R111 R113 GND B R106 R107 10K/NC R109 10K/NC R112 10K/NC R114 +5V 10K PWM1/BOOT4/VOL 10K UART_DO/BOOT3 10K SPI_DO/BOOT2 PWM1 U_DO S_DO SPI_CLK/BOOT1 10K SPI_CSn/BOOT0 10K 1 2 BAT54C Component top view FB29 L1206 OCM 20 bit ADD mode In ckt debug on DDC_CH2 Int OSC OCM 24 bit ADD mode In ckt debug on DDC_CH1 Ext OSC S_CLK S_CSn Lo Normal Lo Lo Debug Hi Hi Test A Lo Hi Test B Hi RX2+ 109 RX2- 110 RX1+ 112 RX1- 113 RX0+ 117 RX0- 118 RXC+ 120 RXC- 121 3.3V_AVDD R110 250R 1% 106 GPIO24/MENU GPIO25/SEL GPIO26/POWER GPIO27/DOWN GPIO28/UP GPIO29/RIGHT GPIO30/LEFT/LED_G GPIO31/KEYPAD GPIO24/MENU GPIO25/SEL GPIO26/POWER GPIO27/DOWN GPIO28/UP GPIO29/RIGHT GPIO30/LEFT/LED_G GPIO31/KEYPAD 176 177 178 179 180 181 182 183 184 RX2+ RX2RX1+ RX1RX0+ RX0RXC+ RXC- REXT GPIO_24/VD[0] GPIO_25/VD[1] GPIO_26/VD[2] GPIO_27/VD[3] GPIO_28/VD[4] GPIO_29/VD[5] GPIO_30/VD[6] GPIO_31/VD[7] VCLK Cable_detect LBADC1 LBADC3 LBADC1 GND GPIO3/LED_ORANGE GPIO4/LED_BLUE R221 0R R226 0R R227 0R SPI_CSn/BOOT0 187 SPI_CLK/BOOT1 188 SPI_DI 189 SPI_DO/BOOT2 190 J1 1 2 3 4 5 6 167 168 169 171 GPIO_3/LED_R 194 GPIO_4/LED_G 197 198 199 200 CON6 GPIO_3/LED_R GPIO_4/LED_G SPI_CSn/BOOT[0] SPI_CLK/BOOT[1] SPI_DI SPI_DO/BOOT[2] LBADC_IN3 LBADC_IN2 LBADC_IN1 JTAG_BS_EN GPIO_3/JTAG_RESET GPIO_4/JTAG_TDO GPIO_5/JTAG_TDI GPIO_6/JTAG_CLK GPIO_7/JTAG_MODE CVDD_1.8 CVDD_1.8 CVDD_1.8 CVDD_1.8 CVDD_1.8 CVDD_1.8 CVDD_1.8 55 92 102 134 174 195 206 RVDD_3.3 RVDD_3.3 RVDD_3.3 RVDD_3.3 RVDD_3.3 RVDD_3.3 RVDD_3.3 RVDD_3.3 17 25 36 54 93 127 185 207 +3.3_ADCV FLI5961 LBADC_VDD_3.3 170 C208 0.1uF/6 VCC 16 166 LBADC_RTN/GND VSSA_DVI VSS_DVI VSSA_DVI VSSA_DVI VSSA_DVI 105 122 114 116 108 R243 0R/NC DDC_SCL_VGA DDC_SDA_VGA A R244 AGND 0R/NC R238 10K R128 10K C189 0.1uF R239 100R 100R R240 C185 100pF U6 14 15 X Y C183 4 Z 100pF GND X0 X1 12 13 Y0 Y1 2 1 Z0 Z1 5 3 GNDGND 7 VEE 8 GND INH A 6 11 B C 10 9 74HCT4053 GND R241 100K 0R R246 0R/NC R248 0R R247 0R/NC R249 UART_DI UART_D0_IN R242 0R GND UART_SEL GND ADD 4053 For UART 11/23/2005 5 GPIO5/FLASH_W P VSSA_ADC VSSA_ADC VSSA_ADC VSSA_ADC VSSA_ADC 157 GND1_ADC 161 VSS_RPLL 138 143 145 149 156 +3.3_DVDD R120 10K GND U8 1 2 3 4 CE# SO WP# VSS VCC HOLD# SCK SI 8 7 6 5 PM25LV040 R216 0R/NC C105 R121 0.1uF 10K GND PLLGND SPI_CLK/BOOT1 SPI_DO/BOOT2 SPI_DI SPI_CSn/BOOT0 GPIO5/FLASH_W P AGND GND 4 3 16 24 37 56 91 103 126 135 173 186 196 205 CRVSS CRVSS CRVSS CRVSS CRVSS CRVSS CRVSS CRVSS CRVSS CRVSS CRVSS CRVSS AVDD_LV_3.3 AVDD_OUT_LV_3.3 AVDD_OUT_LV_3.3 AVDD_OUT_LV_3.3 60 62 74 86 2 1 +3.3_RVDD +3.3_DVDD FB2 L1206 +3.3_RVDD C57 0.1uF C58 0.1uF C59 0.1uF C60 0.1uF C61 0.1uF C62 0.1uF C63 0.1uF C64 C65 0.1uF 22uF/10V C66 47uF/10V GND M1 +3.3_AVDD FB4 L1206 M2 C48 0.1uF R72 R73 C73 0.1uF R74 R75 0R/NC 0R M_B2 0R/NC 0R M_B3 GPIO_13/B7 GPIO_12/B6 GPIO_11/B5 GPIO_10/B4 90 89 88 87 CH0N_LV_O/B3 CH0P_LV_O/B2 CH1N_LV_O/B1 CH1P_LV_O/B0 CH2N_LV_O/G7 CH2P_LV_O/G6 CLKN_LV_O/G5 CLKP_LV_O/G4 CH3N_LV_O/G3 CH3P_LV_O/G2 84 83 82 81 80 79 78 77 76 75 CH0N_LV_E/G1 CH0P_LV_E/G0 CH1N_LV_E/R7 CH1P_LV_E/R6 CH2N_LV_E/R5 CH2P_LV_E/R4 CLKN_LV_E/R3 CLKP_LV_E/R2 CH3N_LV_E/R1 CH3P_LV_E/R0 72 71 70 69 68 67 66 65 64 63 GPIO_17/DVS GPIO_16/DHS GPIO_15/DEN GPIO_14/DCLK 97 96 95 94 PPWR PBIAS 58 59 GPIO_9/PWM3/BOOT[7] GPIO_8/PWM2/BOOT[6] PW M1/BOOT[4] PW M0/BOOT[5] 204 203 202 201 GPIO_23/INT0 GPIO_22/INT1 175 172 GPIO_21/SDA_1(2W_Mst) GPIO_20/SCL_1(2W_Mst) GPIO_19/SDA_0(2W_Mst) GPIO_18/SCL_0(2W_Mst) 101 100 99 98 GPIO_2 193 UART_SEL C75 0.1uF C76 0.1uF C77 0.1uF C78 C79 0.1uF 22uF/10V C80 47uF/10V LV_O0 LV_O1 LV_O2 LV_O3 LV_O4 LV_O5 LV_O6 LV_O7 LV_O8 LV_O9 LV_E0 LV_E1 LV_E2 LV_E3 LV_E4 LV_E5 LV_E6 LV_E7 LV_E8 LV_E9 LV_O[0..9] LV_E[0..9] PPWR PBIAS GPIO16_EDID_A GPIO15_EDID_D GPIO14_EDID_DA GPIO_9/PW M3/BOOT7 GPIO_8/PW M2/BOOT6 PWM1/BOOT4/VOL PWM0/BOOT5 MUTE STBY EDID_SEL HDP LV_O[0..9] LV_E[0..9] GND +3.3_DVDD 10K R236 GPIO17_PANCUR PPWR PBIAS PWM1 PWM0/BOOT5 MUTE STBY EDID_SEL HDP MPWR MPWR 10K/NC 10K 10K 10K M3 M4 M5 M6 M7 M8 M9 M10 GND C74 0.1uF R76 R77 C91 0.1uF R78 R79 C92 0.1uF R80 R82 C93 0.1uF R83 R84 C94 0.1uF R85 R86 C95 0.1uF R87 R89 C98 0.1uF R90 R91 C99 0.1uF R93 R94 0R/NC 0R M_B4 D 0R/NC 0R M_B8 0R/NC 0R M_A1 0R/NC 0R M_A2 0R/NC 0R M_A7 0R/NC 0R M_A15 0R/NC 0R M_ADD5 0R/NC 0R RAS# +3.3_DVDD C R100 R101 R102 R103 DQ0_B DQ1_B DQ2_B DQ3_B DQ4_B DQ5_B DQ6_B DQ7_B DQ8_B DQ9_B DQ10_B DQ11_B DQ12_B DQ13_B DQ14_B DQ15_B 45 44 43 42 41 40 39 38 53 52 51 50 49 48 47 46 DQ0_A DQ1_A DQ2_A DQ3_A DQ4_A DQ5_A DQ6_A DQ7_A DQ8_A DQ9_A DQ10_A DQ11_A DQ12_A DQ13_A DQ14_A DQ15_A 7 6 5 4 3 2 1 208 15 14 13 12 11 10 9 8 A10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 35 34 33 32 31 30 29 28 27 26 23 DQM MCLK BA RAS# CAS# WE# 57 22 21 20 19 18 SCAN_EN VBUFC_RPLL 104 159 M_B0 M_B1 M1 M2 M3 M_B5 M_B6 M_B7 M4 M_B9 M_B10 M_B11 M_B12 M_B13 M_B14 M_B15 M_A0 M5 M6 M_A3 M_A4 M_A5 M_A6 M7 M_A8 M_A9 M_A10 M_A11 M_A12 M_A13 M_A14 M8 M_ADD10 M_ADD0 M_ADD1 M_ADD2 M_ADD3 M_ADD4 M9 M_ADD6 M_ADD7 M_ADD8 M_ADD9 M10 SP1 SP2 M_B3 M_B2 M_B1 M_B0 M_B7 M_B6 M_B5 M_B4 RN14 3 2 1 RN24 3 2 1 5 33RB8P 6 7 8 5 33RB8P 6 7 8 DQ_B_3 DQ_B_2 DQ_B_1 DQ_B_0 DQ_B_7 DQ_B_6 DQ_B_5 DQ_B_4 MUTE STBY EDID_SEL MPWR M_B11 M_B10 M_B9 M_B8 M_B15 M_B14 M_B13 M_B12 RN34 3 2 1 RN44 3 2 1 5 33RB8P 6 7 8 5 33RB8P 6 7 8 DQ_B_11 DQ_B_10 DQ_B_9 DQ_B_8 DQ_B_15 DQ_B_14 DQ_B_13 DQ_B_12 M_A3 M_A2 M_A1 M_A0 M_A7 M_A6 M_A5 M_A4 RN54 3 2 1 RN64 3 2 1 5 33RB8P 6 7 8 5 33RB8P 6 7 8 DQ_A_3 DQ_A_2 DQ_A_1 DQ_A_0 DQ_A_7 DQ_A_6 DQ_A_5 DQ_A_4 DQ_B_[0..15] DQ_A_[0..15] A[0..10] DQ_B_[0..15] DQ_A_[0..15] A[0..10] M_A11 RN74 5 33RB8P DQ_A_11 B M_A10 3 6 DQ_A_10 M_A9 2 7 DQ_A_9 M_A8 1 8 DQ_A_8 M_A15 RN84 5 33RB8P DQ_A_15 M_A14 3 6 DQ_A_14 M_A13 2 7 DQ_A_13 M_A12 1 8 DQ_A_12 M_ADD2 RN94 M_ADD1 3 M_ADD0 2 M_ADD10 1 5 33RB8P A2 6 A1 7 A0 8 A10 M_ADD6 M_ADD5 M_ADD4 M_ADD3 RN140 3 2 1 5 33RB8P A6 6 A5 7 A4 8 A3 M_ADD9 M_ADD8 M_ADD7 RN141 3 2 1 5 33RB8P A9 6 A8 7 A7 8 RAS# R115 0R R116 0R R117 0R R118 0R R119 0R DQM MCLK BA RAS# CAS# WE# AVSS_LV AVSS_OUT_LV AVSS_OUT_LV 61 73 85 C104 22pF/NC GND A PROJECT : WDTB Techview Inc. TitTleitle 03. FLI5961 SizSeize DaDtea:te: Document Number SCHEMATIC1 Monday, January 02, 2006 Rev WDTB ShSeheet et 3 Rev C2A of 8 2 1