Acer Aspire 4810TZ Aspire 4810T, 4810TG, 4810TZ and 4410TZG Service Guide - Page 92

Post Code Table

Page 92 highlights

Post Code Table POST Code 01 02 04 05 08 09 0A 0D 0E 10 11 12 13 14 2F 32 33 34 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 46 46 47 48 4A 4B 4D 4D 4E 84 Description Prepare PEI Event Log service (bios debug purpose) OEM service Initialization (bios debug purpose) Status code report service initialization (bios debug purpose) CPU IO and PCI IO (bios debug purpose) CPU Initialization PC Init at stage 1 (SB related init) Firmware Flash Device (for BIOS ROM) Read Services (bios debug purpose) PC Init at stage 2 (NB related init) SMbus Memory Initialization Restore system configuration for S3 resume (bios debug purpose) Clock generator Initialization Provide TPM Presence policy (bios debug purpose) TPM Module Extract BIOS ROM to memory Prepare services for S3 resume (bios debug purpose) Prepare services for S3 resume (bios debug purpose) 8254 timer chip initialization PCX decoder CPU Initialization Prepare stall (delay) related services (bios debug purpose) BIOS ROM reclaims relative Install EFI Runtime Protocol (bios debug purpose) The counter for System boot times (bios debug purpose) Watchdog timer service initialization (bios debug purpose) EFI driver format verification (bios debug purpose) Provide CPU IO protocol service (bios debug purpose) Provide reset service (bios debug purpose) Real Time Clock Initialization Status code report service initialization (bios debug purpose) Firmware Flash Device (for BIOS ROM) Read/Write Services Firmware Flash Device Read/Write for BIOS ROM recovery (bios debug purpose) PC Init at stage 1 (SB related init) PCI Host Bridge Initialization PCI-E Initialization SB Controller Initialization SATA Controller Initialization SM Bus Initialization NB Initialization ISA Bus Initialization ISA Serial Device Initialization Chapter 4

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