Acer Aspire 5741 Service Guide - Page 153

Post Codes These tables describe the POST codes and descriptions during the POST. Post Code Range SEC PEI DXE BDS SMM S3 ASL Phase PostBDS InsydeH2ODDT™ Reserve OEM Reserve Reserved POST Code Range 0x01 - 0x0F 0x70 - 0x9F 0x40 - 0x6F 0x10 - 0x3F 0xA0 - 0xBF 0xC0 - 0xCF 0x51 - 0x55 0xE1 - 0xE4 0xF9 - 0xFE 0xD0 - 0xD7 0xE8 - 0xEB 0xD8 - 0xE0 0xE5 - 0xE7 0xEC - 0xF8 SEC Phase POST Code Table Functionality Name (Include\ PostCode.h) SEC_SYSTEM_POWER_ON Phase SEC SEC_BEFORE_MICROCODE_PATCH SEC_AFTER_MICROCODE_PATCH SEC_ACCESS_CSR SEC_GENERIC_MSRINIT SEC_CPU_SPEEDCFG SEC_SETUP_CAR_OK SEC_FORCE_MAX_RATIO SEC SEC SEC SEC SEC SEC SEC SEC_GO_TO_SECSTARTUP SEC_GO_TO_PEICORE SEC SEC Post Code 1 2 3 4 5 6 7 8 9 0A Description CPU power on and switch to Protected mode Patching CPU microcode Setup Cache as RAM PCIE MMIO Base Address initial CPU Generic MSR initialization Setup CPU speed Cache as RAM test Tune CPU frequency ratio to maximum level Setup BIOS ROM cache Enter Boot Firmware Volume NOTE: The color bar items indicate 3rd party related functions that are platorm dependent. Chapter 4 143