Biostar M6VLQ M6VLQ user's manual - Page 49
Advanced Chipset Features
View all Biostar M6VLQ manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 49 highlights
Chapter 2 BIOS Setup 2.4 Advanced Chipset Features This submenu allows you to configure the specific features of the chipset installed on your system. This chipset manages bus speeds and access to system memory resources, such as DRAM and external cache. It also coordinates communications with the PCI bus. The default settings that came with your system have been optimized and therefore should not be changed unless you are suspicious that the settings have been changed incorrectly. Figure 4. Advanced Chipset Setup Bank Interleave DRAM Clock When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. The Choices: By SPD (default), HCLK-33M, HCLK+33M, Host CLK. 2-13
Chapter 2
BIOS Setup
2-13
2.4 Advanced Chipset Features
This submenu allows you to configure the specific features of the chipset installed on
your system. This chipset manages bus speeds and access to system memory
resources, such as DRAM and external cache.
It also coordinates communications
with the PCI bus. The default settings that came with your system have been
optimized and therefore should not be changed unless you are suspicious that the
settings have been changed incorrectly.
±
Figure 4. Advanced Chipset Setup
Bank Interleave
DRAM Clock
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing.
The Choices: By SPD
(default), HCLK-33M, HCLK+33M, Host CLK.