Biostar M7VIT M7VIT BIOS setup guide - Page 16

M7VIT BIOS Setup PCI1 Master 0 WS Write When enabled, writes to the PCI bus are executed with zero-wait states. The Choices: Enabled (default), Disabled. PCI2 Master 0 WS Write When enabled, writes to the AGP bus are executed with zero-wait states. The Choices: Enabled (default), Disabled. PCI1 Post Write When Enabled, CPU writes are allowed to post on the PCI bus. The Choices: Enabled (default), Disabled. PCI2 Post Write When Enabled, CPU writes are allowed to post on the AGP bus. The Choices: Enabled (default), Disabled. VLink 8X Support The Choices: Enabled (default), Disabled. PCI Delay Transaction The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification. The Choices: Enabled (default), Disabled. Memory Hole When enabled, you can reserve an area of system memory for ISA adapter ROM. When this area is reserved, it cannot be cached. Refer to the user documentation of the peripheral you are installing for more information. The Choices: Disabled (default), 15M - 16M. System BIOS Cacheable Selecting the "Enabled" option allows caching of the system BIOS ROM at F0000h-FFFFFh, which can improve system performance. However, any programs writing to this area of memory will cause conflicts and result in system errors. The Choices: Enabled, Disabled (default). Video RAM Cacheable Enabling this option allows caching of the video RAM, resulting in better system performance. However, if any program writes to this memory area, a system error may result. The Choices: Enabled, Disabled (default). 15