D-Link DSN-2100-10 Hardware Reference Guide for DSN-2100-10 Valid for fir - Page 27

Requirement PC2700/DDR333 speed ECC X8 RAMs Registered Buffered Organization Table A-1. xStack Storage Array DIMM Specifications Description SDRAMs must be JEDEC compliant and DDR333 capable, with a CAS latency of 2.5. PC2100/DDR400 speed DIMMs can be used if they support a 2.5 CAS latency when operating at DDR333 speed. DIMMs must be organized as x72 bits wide, allowing support for ECC. DIMMs must use 8-bit wide DRAMs that can support data mask (DM) signals. DIMMs that use 4-bit-wide DRAMs do not provide DM signals and cannot be used. DIMMs must be registered as per the JEDEC specification for registered DIMMs. DIMMs must be buffered as per the JEDEC specification for buffered DIMMs. Conforming DIMM organizations are shown in Table A-2.. DIMM 0 (J38) System Memory Module 256MB 256MB 256MB 256MB DIMM 1 (J39) System Memory Module 256MB 256MB 256MB 256MB Table A-2. DIMM Organization Total System Memory 512MB 512MB 512MB 512MB DIMM 2 (J36) Buffer/Cache Memory Module 256MB 512MB 1GB 2GB DIMM 3 (J37) Buffer/Cache Memory Module 256MB 512MB 1GB 2GB Total Buffer/Cache Memory 512MB 1GB 2GB 4GB Total Memory 1GB 1.5GB 2.5GB 4.5GB DSN-2100 Hardware Reference Guide 27