EVGA 780i User Manual - Page 61

FSB QDR, MHz, MEM DDR, MHz, Memory Timing Setting, Optimal - manual

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780i 3-Way SLI Motherboard ‰ FSB (QDR), MHz Use the + or - keys to scroll through new values for the CPU FSB frequency or type in a new value. Note that the Actual FSB (QDR) reflects the actual frequency that takes effect on a reboot. ‰ MEM (DDR), MHz Use the + or - keys to scroll through new values for the memory frequency or type in a new value. Note that the Actual MEM (DDR) reflects the actual frequency that takes effect when the system reboots. ‰ Memory Timing Setting Press Enter to display the Memory Timing Setting menu. Use this menu to set optimal timings or to manually enter timings. Phoenix - AwardBIOS CMOS Setup Utility Memory Timing Setting Parameters Settings Current Value Item Help Memory Timing Setting [Optimal] x tCL (CAS Latency) Auto(5) x tRDC Auto(7) x tRP Auto(7) x tRAS Auto(23) x Command Per Clock (CDM) Auto(2T) ** Advanced Memory Settings ** x tRRD Auto(4) x tRC Auto(28) x tWR Auto(7) x tWTR Auto(10) x tREF Auto 5 5 5 18 1T 3 22 5 9 6.1uS Main Level `` Select [Expert] to enter timings manually EVGA 50 :Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help[ F5: Previous Values F7:Defaults ¾ Optimal Use the Page Up and Page Down keys to select Optimal. Optimal

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780i 3-Way SLI Motherboard
EVGA
50
FSB (QDR), MHz
Use the
+
or
–
keys to scroll through new values for the CPU FSB frequency
or type in a new value. Note that the
Actual FSB (QDR)
reflects the actual
frequency that takes effect on a reboot.
MEM (DDR), MHz
Use the
+
or
–
keys to scroll through new values for the memory frequency
or type in a new value. Note that the
Actual MEM (DDR)
reflects the actual
frequency that takes effect when the system reboots.
Memory Timing Setting
Press
Enter
to display the Memory Timing Setting menu. Use this menu to
set optimal timings or to manually enter timings.
Optimal
Use the
Page Up
and
Page Down
keys to select
Optimal.
Optimal
:Move
Enter:Select
+/-/PU/PD:Value
F10:Save
ESC:Exit
F1:General Help[
F5: Previous Values
F7:Defaults
Parameters
Settings Current Value
Memory Timing Setting
[
Optimal
]
x
tCL (CAS Latency)
Auto(5)
5
x
tRDC
Auto(7)
5
x
tRP
Auto(7)
5
x
tRAS
Auto(23)
18
x
Command Per Clock (CDM)
Auto(2T)
1T
** Advanced Memory Settings **
x
tRRD
Auto(4)
3
x
tRC
Auto(28)
22
x
tWR
Auto(7)
5
x
tWTR
Auto(10)
9
x
tREF
Auto
6.1uS
Item Help
Main Level
Select [Expert] to
enter timings manually
Phoenix – AwardBIOS CMOS Setup Utility
Memory Timing Setting