Epson Apex 386SX/20 Canadian Product User Manual - Page 116

Real Address Mode, System Timers, Intel 8254-2 chip. These are channels 0 through 2 defined as follows

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Real Address Mode In real mode the 386SX microprocessor operates as a very fast 8086, but with a 32-bit extension if desired. Real mode is required primarily to set up the processor for protected mode operation. The segmentation unit shifts the selector left four bits and adds the result to the effective address to form the linear address. This linear address is limited to 1 megabyte. In addition, real mode has no paging capability. System Timers The system has three programmable timer/counters controlled by the Intel 8254-2 chip. These are channels 0 through 2 defined as follows: Table 6 -1: Channel 0 Table 6-2: Channel 1 NOTE: Channel 1 is programmed to generate a 15 microsecond signal. Table 6-3: Channel 2 18 Chapter 6: Appendix

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Real Address Mode
In real mode the 386SX microprocessor operates as a very fast 8086,
but with a 32-bit extension if desired. Real mode is required primarily
to set up the processor for protected mode operation.
The segmentation unit shifts the selector left four bits and adds the
result to the effective address to form the linear address. This linear
address is limited to 1 megabyte. In addition, real mode has no paging
capability.
System Timers
The system has three programmable timer/counters controlled by the
Intel 8254-2 chip. These are channels 0 through 2 defined as follows:
Table 6 -1: Channel 0
Table 6-2: Channel 1
NOTE: Channel 1 is programmed to generate a 15 microsecond
signal.
Table 6-3: Channel 2
18
Chapter 6: Appendix