Gigabyte GA-790XTA-UD4 Manual - Page 40

CPU Host Clock Control, CPU Frequency MHz, Set Memory Clock, DCTs Mode, DDR3 Timing Items, MB

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Page 40 highlights

DRAM Configuration CMOS Setup Utility-Copyright (C) 1984-2009 Award Software DRAM Configuration CPU Host Clock Control x CPU Frequency(MHz) Set Memory Clock x Memory Clock DCTs Mode DDR3 Timing Items x CAS# latency x RAS to CAS R/W Delay x Row Precharge Time x Minimum RAS Active Time x 1T/2T Command Timing x TwTr Command Delay x Trfc0 for DIMM1 x Trfc2 for DIMM2 x Trfc1 for DIMM3 x Trfc3 for DIMM4 x Write Recovery Time x Precharge Time x Row Cycle Time [Auto] 200 [Auto] x6.66 [Unganged] [Auto] Auto Auto Auto Auto Auto Auto Auto Auto Auto Auto Auto Auto Auto 1333Mhz SPD 9T 9T 9T 24T -5T 110ns ---10T 5T 33T Auto 9T 9T 9T 24T -5T 110ns ---10T 5T 33T Item Help Menu Level  Move Enter: Select F5: Previous Values +/-/PU/PD: Value F10: Save F6: Fail-Safe Defaults ESC: Exit F1: General Help F7: Optimized Defaults CMOS Setup Utility-Copyright (C) 1984-2009 Award Software DRAM Configuration x RAS to RAS Delay CHA ProcOdt CHA DQS drive strength CHA Data drive strength CHA MEMCLK drive strength CHA Add/Cmd drive strength CHA CS/ODT drive strength CHA CKE drive strength CHB ProcOdt CHB DQS drive strength CHB Data drive strength CHB MEMCLK drive strength CHB Add/Cmd drive strength CHB CS/ODT drive strength CHB CKE drive strength Bank Interleaving Channel interleave Auto [Auto] [Auto] [Auto] [Auto] [Auto] [Auto] [Auto] [Auto] [Auto] [Auto] [Auto] [Auto] [Auto] [Auto] [Enabled] [Enabled] 4T 4T 60 ohms 1.0x 1.0x 1.25x 1.5x 1.5x 1.5x 60 ohms 1.0x 1.0x 1.25x 1.5x 1.5x 1.5x Item Help Menu Level  Move Enter: Select F5: Previous Values +/-/PU/PD: Value F10: Save F6: Fail-Safe Defaults ESC: Exit F1: General Help F7: Optimized Defaults CPU Host Clock Control, CPU Frequency (MHz), Set Memory Clock, Memory Clock The settings under the four items above are synchronous to those under the same items on the MB Intelligent Tweaker(M.I.T.) main menu. DCTs Mode Allows you to set memory control mode. Ganged Sets memory control mode to single dual-channel. Unganged Sets memory control mode to two single-channel. (Default) DDR3 Timing Items Manual allows all DDR3 Timing items below to be configurable. Options are: Auto (default), Manual. BIOS Setup - 40 -

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BIOS Setup
- 40 -
CPU Host Clock Control, CPU Frequency (MHz), Set Memory Clock, Memory Clock
The settings under the four items above are synchronous to those under the same items on the
MB In-
telligent Tweaker(M.I.T.)
main menu.
DCTs Mode
Allows you to set memory control mode.
Ganged
Sets memory control mode to single dual-channel.
Unganged
Sets memory control mode to two single-channel. (Default)
DDR3 Timing Items
Manual
allows all DDR3 Timing items below to be configurable.
Options are: Auto (default), Manual.
DRAM Configuration
CMOS Setup Utility-Copyright (C) 1984-2009 Award Software
DRAM Configuration
CPU Host Clock Control
[Auto]
x
CPU Frequency(MHz)
200
Set Memory Clock
[Auto]
x
Memory Clock
x6.66
1333Mhz
DCTs Mode
[Unganged]
DDR3 Timing Items
[Auto]
SPD
Auto
x
CAS# latency
Auto
9T
9T
x
RAS to CAS R/W Delay
Auto
9T
9T
x
Row Precharge Time
Auto
9T
9T
x
Minimum RAS Active Time
Auto
24T
24T
x
1T/2T Command Timing
Auto
--
--
x
TwTr Command Delay
Auto
5T
5T
x
Trfc0 for DIMM1
Auto
110ns
110ns
x
Trfc2 for DIMM2
Auto
--
--
x
Trfc1 for DIMM3
Auto
--
--
x
Trfc3 for DIMM4
Auto
--
--
x
Write Recovery Time
Auto
10T
10T
x
Precharge Time
Auto
5T
5T
x
Row Cycle Time
Auto
33T
33T
higf
: Move
Enter: Select
+/-/PU/PD: Value
F10: Save
ESC: Exit
F1: General Help
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Item Help
Menu Level
CMOS Setup Utility-Copyright (C) 1984-2009 Award Software
DRAM Configuration
higf
: Move
Enter: Select
+/-/PU/PD: Value
F10: Save
ESC: Exit
F1: General Help
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Item Help
Menu Level
x
RAS to RAS Delay
Auto
4T
4T
CHA ProcOdt
[Auto]
60 ohms
CHA DQS drive strength
[Auto]
1.0x
CHA Data drive strength
[Auto]
1.0x
CHA MEMCLK drive strength
[Auto]
1.25x
CHA Add/Cmd drive strength
[Auto]
1.5x
CHA CS/ODT drive strength
[Auto]
1.5x
CHA CKE drive strength
[Auto]
1.5x
CHB ProcOdt
[Auto]
60 ohms
CHB DQS drive strength
[Auto]
1.0x
CHB Data drive strength
[Auto]
1.0x
CHB MEMCLK drive strength
[Auto]
1.25x
CHB Add/Cmd drive strength
[Auto]
1.5x
CHB CS/ODT drive strength
[Auto]
1.5x
CHB CKE drive strength
[Auto]
1.5x
Bank Interleaving
[Enabled]
Channel interleave
[Enabled]