Gigabyte GA-7IX User Manual - Page 46

System BIOS Cacheable, Video RAM Cacheable, Memory Hole at 15M-16M

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Advanced Chipset Features BIOS Setup CMOS Setup Utility-Copyright( C ) 1984-1999 Award Software Advanced Chipset Features System BIOS Cacheable Video RAM Cacheable Memory Hole At 15M−16M AGP Aperture Size (MB) K7 CLK_CTL Select SDRAM ECC Setting SDRAM PH Limit SDRAM Idle Limit SDRAM Timing Configuration * SDRAM Trc Timing Value * SDRAM Trp Timing Value * SDRAM Tras Timing Value * SDRAM CAS Latency * SDRAM Trcd Timing Value Enabled Enabled Disabled 64 Optimal Disabled 32 Cycle 8 Cycle Auto 8 Cycle 3 Cycle 5 Cycle 3 Cycle 3 Cycle Item Help Menu Level 4 Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults Figure 4: Advanced Chipset Features • System BIOS Cacheable Enabled Enable System BIOS Cacheable. ( Default value ) Disabled Disable System BIOS Cacheable. • Video RAM Cacheable Enabled Enable video RAM Cacheable. ( Default value ) Disabled Disable video RAM Cacheable. • Memory Hole at 15M-16M Enabled Set Address=15-16MB relocate to ISA BUS. Disabled Normal Setting. ( Default value ) 34

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BIOS Setup
34
Advanced Chipset Features
Figure 4: Advanced Chipset Features
•
System BIOS Cacheable
Enabled
Enable System BIOS Cacheable.
( Default value )
Disabled
Disable System BIOS Cacheable.
•
Video RAM Cacheable
Enabled
Enable video RAM Cacheable.
( Default value )
Disabled
Disable video RAM Cacheable.
•
Memory Hole at 15M-16M
Enabled
Set Address=15-16MB relocate to ISA BUS.
Disabled
Normal Setting.
( Default value )
CMOS Setup Utility-Copyright( C ) 1984-1999 Award Software
Advanced Chipset Features
System BIOS Cacheable
Enabled
Item Help
Video RAM Cacheable
Enabled
Memory Hole At 15M
-
16M
Disabled
Menu Level
4
AGP Aperture Size (MB)
64
K7 CLK_CTL Select
Optimal
SDRAM ECC Setting
Disabled
SDRAM PH Limit
32 Cycle
SDRAM Idle Limit
8 Cycle
SDRAM Timing Configuration
Auto
* SDRAM Trc Timing Value
8 Cycle
* SDRAM Trp Timing Value
3 Cycle
* SDRAM Tras Timing Value
5 Cycle
* SDRAM CAS Latency
3 Cycle
* SDRAM Trcd Timing Value
3 Cycle
↑↓→
←
:Move
Enter:Select
+/-/PU/PD:Value
F10:Save
ESC:Exit
F1:General Help
F5:Previous Values
F6:Fail-Safe Defaults
F7:Optimized Defaults