Gigabyte GA-7IX User Manual - Page 47

AGP Aperture Size MB, K7 CLK_CTL Select, SDRAM ECC Setting, SDRAM PH Limit, SDRAM Idle Limit

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7IX Motherboard • AGP Aperture Size (MB) 32 Set AGP Aperture Size to 32. 64 Set AGP Aperture Size to 64. ( Default value ) 128 Set AGP Aperture Size to 128. 256 Set AGP Aperture Size to 256. • K7 CLK_CTL Select Optimal Default Set K7 CLK_CTL Select to Optimal. ( Default value ) Set K7 CLK_CTL Select to Default. • SDRAM ECC Setting Enabled Disabled Enabled SDRAM ECC Setting function. Disabled this function. ( Default value ) • SDRAM PH Limit This function specify the number of consecutive Page-Hit requests to allow before choosing a non-Page-Hit request. 1 Cycle 4 Cycle 32 Cycle 64 Cycle Set SDRAM PH Limit to 1 Cycle. Set SDRAM PH Limit to 4 Cycle. Set SDRAM PH Limit to 32 Cycle. ( Default value ) Set SDRAM PH Limit to 64 Cycle. • SDRAM Idle Limit This function specify the number of idle cycles to wait before precharging an idle bank.(Idle cycles are defined as cycles where no valid request is asserted to the MCT.) 1 Cycle 8 Cycle 32 Cycle 64 Cycle Set SDRAM Idle Limit to 1 Cycle. Set SDRAM Idle Limit to 8 Cycle. ( Default value ) Set SDRAM Idle Limit to 32 Cycle. Set SDRAM Idle Limit to 64 Cycle. 35

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7IX Motherboard
35
•
AGP Aperture Size (MB)
32
Set AGP Aperture Size to 32.
64
Set AGP Aperture Size to 64.
( Default value )
128
Set AGP Aperture Size to 128.
256
Set AGP Aperture Size to 256.
•
K7 CLK_CTL Select
Optimal
Set K7 CLK_CTL Select to Optimal.
( Default value )
Default
Set K7 CLK_CTL Select to Default.
•
SDRAM ECC Setting
Enabled
Enabled SDRAM ECC Setting function.
Disabled
Disabled this function.
( Default value )
•
SDRAM PH Limit
This function specify the number of consecutive Page-Hit requests to allow before
choosing a non-Page-Hit request.
1 Cycle
Set SDRAM PH Limit to 1 Cycle.
4 Cycle
Set SDRAM PH Limit to 4 Cycle.
32 Cycle
Set SDRAM PH Limit to 32 Cycle.
( Default value )
64 Cycle
Set SDRAM PH Limit to 64 Cycle.
•
SDRAM Idle Limit
This function specify the number of idle cycles to wait before precharging an idle bank.(Idle
cycles are defined as cycles where no valid request is asserted to the MCT.)
1 Cycle
Set SDRAM Idle Limit to 1 Cycle.
8 Cycle
Set SDRAM Idle Limit to 8 Cycle.
( Default value )
32 Cycle
Set SDRAM Idle Limit to 32 Cycle.
64 Cycle
Set SDRAM Idle Limit to 64 Cycle.