HP Vectra XU 6/XXX HP Vectra XU - Guide to Optimizing Performance, Not Orderab - Page 61

Dedicated Level-Two, Cache Bus, Cache Coherency

Page 61 highlights

2 Technical Reference The Intel Pentium Pro Processor Dedicated Level-Two Cache Bus The Pentium Pro increases the performance of its level-two cache by accessing it over a dedicated, 64-bit internal bus. This means that accesses to the cache will cause no contention with any operations on the local bus. It also ensures that the level-two cache is able to operate at the full internal clock speed of the processor. Level-two cache bus Level-two cache Processor core Local bus Cache Coherency One important implication of using cache memories is that duplicate copies of data exist in different parts of your PC. With duplicate copies of the same data, a mechanism must be used to ensure coherency between the copies. This is particularly true for dual processor configurations, where duplications can exist not only between a processor cache and memory, but also between the caches in the two processors. The Pentium Pro's level-two data cache is a copy-back cache, meaning that if the processor writes data that produces a cache hit, then that data will be written directly in the level-two cache. The cache will then copy the data back to memory at a later time. Until the cache copies the data back to memory, the copy of the data held in memory is no longer valid. English 55

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75

English
55
2
Technical Reference
The Intel Pentium Pro Processor
Dedicated Level-Two
Cache Bus
The Pentium Pro increases the performance of its level-two cache by
accessing it over a dedicated, 64-bit internal bus. This means that
accesses to the cache will cause no contention with any operations on
the local bus. It also ensures that the level-two cache is able to operate
at the full internal clock speed of the processor.
Cache Coherency
One important implication of using cache memories is that duplicate
copies of data exist in different parts of your PC. With duplicate copies
of the same data, a mechanism must be used to ensure coherency
between the copies. This is particularly true for dual processor
configurations, where duplications can exist not only between a
processor cache and memory, but also between the caches in the two
processors.
The Pentium Pro’s level-two data cache is a copy-back cache, meaning
that if the processor writes data that produces a cache hit, then that
data will be written directly in the level-two cache. The cache will then
copy the data back to memory at a later time. Until the cache copies
the data back to memory, the copy of the data held in memory is no
longer valid.
Level-two cache bus
Processor core
Level-two cache
Local
bus