HP Visualize J5000 HP Visualize B1000, C3000, J5000 Workstation Memory Subsyst - Page 2

With the new HP VISUALIZE UNIX® Workstations family (B1000, C3000, J5000), the customer will find a completely redesigned memory architecture. With this new architecture comes dramatic performance improvements in memory intensive applications over the HP PA-8200-based (C200, C240, J282, J2240) family of workstations. This paper will explain some of the key elements that contribute to the memory performance improvements in the HP VISUALIZE UNIX® Workstations. It will also compare the architecture of the new memory subsystem with that of the HP PA-8200 subsystem. Finally, and most importantly, application performance will be examined in comparison to the HP PA-8200 family of workstations and those of our competitors. Overview of Memory Subsystem The new memory subsystem architecture was designed with the goal of dramatically improving the memory subsystem performance in the HP VISUALIZE UNIX® family of workstations. At the heart of this new architecture are custom HP VLSI and memory DIMMs, which were designed to provide a low latency, high bandwidth memory subsystem. The HP VISUALIZE UNIX® Workstation systems have an idle system memory latency roughly 40% better than that of the HP PA-8200 products, as well as a memory bandwidth two times that of the HP PA-8200 products. The peak memory bandhwidth of the PA-8200 products was 960MB/s; the peak memory bandwidth of the HP VISUALIZE UNIX® Workstations family is 1.92GB/s. The new subsystem was designed using the latest in synchronous DRAM technology, taking advantage of the memory performance benefits inherent to synchronous DRAM. Sophisticated scheduling algorithms were used to help improve the busy system memory latency and to take full advantage of the memory subsystem bandwidth. The system was also designed to allow maximum memory bandwidth with a minimum of memory in the system. An innovative clocking scheme used in the design of the system board and memory DIMMs enabled the memory subsystem to operate at a frequency much higher than typical for the SDRAMs used. All of these features of the new memory system combine to give the customer dramatic improvements in application performance with the new HP VISUALIZE UNIX® Workstations. Key Design Features New Architecture and VLSI Two new chips were designed for the VISUALIZE memory subsystem: The memory controller chip, which also acts as the I/O controller; and a chip which acts as a large data mux (there are 2 of these chips in the system). In comparison, the HP PA-8200 memory subsystem has a master memory controller and slave memory controllers (3 SMCs in a 12 DIMM system and 4 SMCs in a 16 DIMM system), and data mux chips (4 chips in both the 12 and 16 DIMM systems). The leaner architecture greatly improves the idle system 08/23/99 HP VISUALIZE WORKSTATIONS 1