HP rp7440 Site Preparation Guide, Fourth Edition - HP Integrity rx7640 and HP - Page 26

PCI-X/PCIe Backplane

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Table 1-5 PCI-X Slot Types I/O Partition Slot1 Maximum MHz Maximum Peak Ropes Bandwidth Supported Cards PCI Mode Supported 0 8 133 533 MB/s 001 3.3 V PCI or PCI-X Mode 1 7 133 1.06 GB/s 002/003 3.3 V PCI or PCI-X Mode 1 6 266 2.13 GB/s 004/005 3.3 V or 1.5 V PCI-X Mode 2 5 266 2.13 GB/s 006/007 3.3 V or 1.5 V PCI-X Mode 2 4 266 2.13 GB/s 014/015 3.3 V or 1.5 V PCI-X Mode 2 3 266 2.13 GB/s 012/013 3.3 V or 1.5 V PCI-X Mode 2 2 133 1.06 GB/s 010/011 3.3 V PCI or PCI-X Mode 1 1 133 1.06 GB/s 008/009 3.3 V PCI or PCI-X Mode 1 1 8 133 533 MB/s 001 3.3 V PCI or PCI-X Mode 1 7 133 1.06 GB/s 002/003 3.3 V PCI or PCI-X Mode 1 6 266 2.13 GB/s 004/005 3.3 V or 1.5 V PCI-X Mode 2 5 266 2.13 GB/s 006/007 3.3 V or 1.5 V PCI-X Mode 2 4 266 2.13 GB/s 014/015 3.3 V or 1.5 V PCI-X Mode 2 3 266 2.13 GB/s 012/015 3.3 V or 1.5 V PCI-X Mode 2 2 133 1.06 GB/s 010/011 3.3 V PCI or PCI-X Mode 1 1 133 1.06 GB/s 008/009 3.3 V PCI or PCI-X Mode 1 1 Each slot will auto select the proper speed for the card installed up to the maximum speed for the slot. Placing high speed cards into slow speed slots will cause the card to be driven at the slow speed. PCI-X/PCIe Backplane The 16-slot (8 PCI and PCI-X; 8 PCI-Express) mixed PCI-X/PCI-Express ("PCI-X/PCIe") I/O backplane was introduced for the Dual-Core Intel® Itanium® processor 9100 Series release and is heavily leveraged from the PCI-X backplane design. Only the differences will be descibed here.See "I/O Subsystem" (page 23) for common content between the two boards. The PCI-Express I/O backplane comprises two logically independent I/O circuits (partitions) on one physical board. • The I/O chip in cell location zero (0) and its associated four PCI-X ASICs, four PCIe ASICs, and their respective PCI/PCI-X/PCIe slots form PCI-Express I/O partition 0 plus core I/O. • The I/O chip in cell location one (1) and its associated four PCI-X ASICs, four PCIe ASICs, and their respective PCI/PCI-X/PCIe slots form PCI-Express I/O partition 1 plus core I/O. Each PCI/PCI-X slot has a host-to-PCI bridge associated with it, and each PCIe slot has a host-to-PCIe bridge associated with it. A dual slot hot swap controller chip and related logic is also associated with each pair of PCI or PCIe slots. The I/O chip on either cell location 0 or 1 is a primary I/O system interface. Upstream, the I/O chips communicate directly with the cell controller ASIC on the host cell board via a high bandwidth logical connection known as the HSS link.When installed in the SEU chassis within a fully configured system, the ASIC on cell location 0 connects 26 HP Integrity rx7640 Server and HP 9000 rp7440 Server Overview

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Table 1-5 PCI-X Slot Types
PCI Mode Supported
Supported Cards
Ropes
Maximum Peak
Bandwidth
Maximum MHz
Slot
1
I/O Partition
PCI or PCI-X Mode
1
3.3 V
001
533 MB/s
133
8
0
PCI or PCI-X Mode
1
3.3 V
002/003
1.06 GB/s
133
7
PCI-X Mode 2
3.3 V or 1.5 V
004/005
2.13 GB/s
266
6
PCI-X Mode 2
3.3 V or 1.5 V
006/007
2.13 GB/s
266
5
PCI-X Mode 2
3.3 V or 1.5 V
014/015
2.13 GB/s
266
4
PCI-X Mode 2
3.3 V or 1.5 V
012/013
2.13 GB/s
266
3
PCI or PCI-X Mode
1
3.3 V
010/011
1.06 GB/s
133
2
PCI or PCI-X Mode
1
3.3 V
008/009
1.06 GB/s
133
1
PCI or PCI-X Mode
1
3.3 V
001
533 MB/s
133
8
1
PCI or PCI-X Mode
1
3.3 V
002/003
1.06 GB/s
133
7
PCI-X Mode 2
3.3 V or 1.5 V
004/005
2.13 GB/s
266
6
PCI-X Mode 2
3.3 V or 1.5 V
006/007
2.13 GB/s
266
5
PCI-X Mode 2
3.3 V or 1.5 V
014/015
2.13 GB/s
266
4
PCI-X Mode 2
3.3 V or 1.5 V
012/015
2.13 GB/s
266
3
PCI or PCI-X Mode
1
3.3 V
010/011
1.06 GB/s
133
2
PCI or PCI-X Mode
1
3.3 V
008/009
1.06 GB/s
133
1
1
Each slot will auto select the proper speed for the card installed up to the maximum speed for the slot. Placing high
speed cards into slow speed slots will cause the card to be driven at the slow speed.
PCI-X/PCIe Backplane
The 16–slot (8 PCI and PCI-X; 8 PCI-Express) mixed PCI-X/PCI-Express (“PCI-X/PCIe”) I/O
backplane was introduced for the Dual-Core Intel® Itanium® processor 9100 Series release and
is heavily leveraged from the PCI-X backplane design. Only the differences will be descibed
here.See
“I/O Subsystem” (page 23)
for common content between the two boards.
The PCI-Express I/O backplane comprises two logically independent I/O circuits (partitions) on
one physical board.
•
The I/O chip in cell location zero (0) and its associated four PCI-X ASICs, four PCIe ASICs,
and their respective PCI/PCI-X/PCIe slots form PCI-Express I/O partition 0 plus core I/O.
•
The I/O chip in cell location one (1) and its associated four PCI-X ASICs, four PCIe ASICs,
and their respective PCI/PCI-X/PCIe slots form PCI-Express I/O partition 1 plus core I/O.
Each PCI/PCI-X slot has a host-to-PCI bridge associated with it, and each PCIe slot has a
host-to-PCIe bridge associated with it. A dual slot hot swap controller chip and related logic is
also associated with each pair of PCI or PCIe slots. The I/O chip on either cell location 0 or 1 is a
primary I/O system interface. Upstream, the I/O chips communicate directly with the cell controller
ASIC on the host cell board via a high bandwidth logical connection known as the HSS link.When
installed in the SEU chassis within a fully configured system, the ASIC on cell location 0 connects
26
HP Integrity rx7640 Server and HP 9000 rp7440 Server Overview