Intel BLKD945GTPLR Product Specification - Page 52
Refer to Table 14 for the allocation of PIRQ
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Intel Desktop Board D945GTP Technical Product Specification NOTE In PIC mode, the ICH7 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 14 for the allocation of PIRQ lines to IRQ signals in APIC mode. PCI interrupt assignments to the USB ports, Serial ATA ports, and PCI Express ports are dynamic. 52
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Intel Desktop Board D945GTP Technical Product Specification
52
±
NOTE
In PIC mode, the ICH7 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6,
7, 9, 10, 11, 12, 14, and 15).
Typically, a device that does not share a PIRQ line will have a unique
interrupt.
However, in certain interrupt-constrained situations, it is possible for two or more of the
PIRQ lines to be connected to the same IRQ signal.
Refer to Table 14 for the allocation of PIRQ
lines to IRQ signals in APIC mode.
PCI interrupt assignments to the USB ports, Serial ATA ports, and PCI Express ports are dynamic.