Intel DH77EB Technical Product Specification - Page 79
Error Messages and Beep Codes, Port 80 Code, Progress Code Enumeration - cpu support
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Error Messages and Beep Codes Table 49. Port 80h POST Codes (continued) Port 80 Code Progress Code Enumeration PEI after MRC 0x2A Start to Program MTRR Settings 0x2B Done Programming MTRR Settings PEIMs/Recovery 0x31 Crisis Recovery has initiated 0x33 Loading recovery capsule 0x34 0x41 0x42 0x43 Start recovery capsule/ valid capsule is found CPU Initialization CPU PEI Phase Begin CPU PEI Init XMM instruction enabling End CPU PEI Init CPU PEI SMM Phase 0x44 Begin CPU SMM Init smm relocate bases 0x45 Smm relocate bases for APs 0x46 End CPU SMM Init CPU DXE Phase 0x47 CPU DXE Phase begin 0x48 Refresh memory space attributes according to MTRRs 0x49 Load the microcode if needed 0x4A 0x4B Initialize strings to HII database Initialize MP Support 0x4C 0x4D CPU DXE Phase End CPU DXE SMM Phase CPU DXE SMM Phase begin 0x4E Relocate SM bases for all APs 0x4F CPU DXE SMM Phase end IO BUSES 0x50 Enumerating PCI buses 0x51 Allocating resources to PCI bus 0x52 Hot Plug PCI controller initialization USB 0x58 Resetting USB bus 0x59 Reserved for USB ATA/ATAPI/SATA 0x5A 0x5B Resetting PATA/SATA bus and all devices Reserved for ATA continued 79