Intel Q6600 Data Sheet

Intel Q6600 - Processor - 1 x Core 2 Quad Manual

Get Intel Q6600 - Processor - 1 x Core 2 Quad PDF manuals and user guides
UPC - 675900891401
View all Intel Q6600 manuals
Add to My Manuals
Save this manual to your list of manuals

Intel Q6600 manual content summary:

  • Intel Q6600 | Data Sheet - Page 1
    Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ Sequence Datasheet -on 65 nm Process in the 775-land LGA Package supporting Intel® 64 architecture and Intel® Virtualization Technology± August 2007 Document Number: 315592-005
  • Intel Q6600 | Data Sheet - Page 2
    / processor_number for details. Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on
  • Intel Q6600 | Data Sheet - Page 3
    Contents 1 Introduction ...9 1.1 Terminology ...9 1.1.1 Processor Terminology 10 1.2 References ...11 2 Electrical Specifications 13 2.1 Power and Ground Lands 13 2.2 Decoupling Guidelines 13 2.2.1 VCC Decoupling 13 2.2.2 VTT Decoupling 13 2.2.3 FSB Decoupling 14 2.3 Voltage Identification
  • Intel Q6600 | Data Sheet - Page 4
    90 7.2.1 Fan Heatsink Power Supply 90 7.3 Thermal Specifications 92 7.3.1 7.3.2 7.3.3 Boxed Processor Cooling Requirements 92 Fan Speed Control Operation (Intel® Core™2 Extreme processors only) .........94 Fan Speed Control Operation (Intel® Core™2 Quad processor 94 8 Debug Tools
  • Intel Q6600 | Data Sheet - Page 5
    (Top View 89 25 Space Requirements for the Boxed Processor (Overall View 89 26 Boxed Processor Fan Heatsink Power Cable Connector Description 91 27 Baseboard Power Header Placement Relative to Processor Socket 92 28 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View 93 29
  • Intel Q6600 | Data Sheet - Page 6
    26 16 BSEL[2:0] Frequency Table for BCLK[1:0 27 17 Front Side Bus Differential BCLK Specifications 28 18 FSB Differential Clock Specifications (1066 MHz FSB 28 19 FSB Differential Clock Specifications (1333 MHz FSB 29 20 Processor Loading Specifications 35 21 Package Handling Guidelines
  • Intel Q6600 | Data Sheet - Page 7
    release • Added specifications for the Intel® Core™2 Quad Processor Q6600 • Updated Table 8, "Signal Characteristics". • Updated VTT_SEL description in Table 24. • Updated Table 29, "Fan Heatsink Power and Signal Specifications". • Added specifications for the Intel® Core™2 Quad Processor Q6700
  • Intel Q6600 | Data Sheet - Page 8
    to be made between performance and power consumption. The Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence also include the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as
  • Intel Q6600 | Data Sheet - Page 9
    and Intel® Core™2 quad processor Q6000 sequence are the first desktop quad-core processors that combine the performance and power efficiencies of four low-power microarchitecture cores to enable a new level of multi-tasking, multi-media, and gaming experiences. They are 64-bit processors that
  • Intel Q6600 | Data Sheet - Page 10
    processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O. Processor Terminology Commonly used terms are explained here for clarification: • Intel® Core™2 Extreme quad-core processor QX6000 sequence - Quad core processor
  • Intel Q6600 | Data Sheet - Page 11
    Quad-Core Processor and Intel® Core™2 Quad Processor Thermal and Mechanical Design Guidelines Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket Balanced Technology Extended (BTX) System Design Guide Intel® Virtualization Technology Specification
  • Intel Q6600 | Data Sheet - Page 12
    Introduction 12 Datasheet
  • Intel Q6600 | Data Sheet - Page 13
    for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands, that meets the VTT specifications outlined in Table 4. Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large
  • Intel Q6600 | Data Sheet - Page 14
    default VID settings. This is reflected by the VID Range values provided in Table 4. Refer to the Intel® Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel® Core™2 Quad Processor Q6000 Sequence Specification Update for further details on specific valid core frequency and VID values of the
  • Intel Q6600 | Data Sheet - Page 15
    Electrical Specifications Table 2. Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX 1 1 1 1 0 1 0.8500 1 1 1 1 0 0 0.8625 1 1 1 0 1 1 0.8750 1 1 1 0 1 0 0.8875 1 1 1 0 0 1 0.9000 1 1 1 0 0 0 0.9125 1 1 0 1 1 1 0.9250 1 1 0 1 1
  • Intel Q6600 | Data Sheet - Page 16
    as GTL+ termination is provided on the processor silicon. However, see Table 7 for details on GTL+ signals that power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard
  • Intel Q6600 | Data Sheet - Page 17
    Ratings Symbol Parameter Min Max Unit Notes1,2 VCC Core voltage with respect to VSS -0.3 1.55 V - VTT FSB termination voltage with respect to VSS -0.3 1.55 V - TC Processor case temperature See Chapter 5 See Chapter 5 °C - TSTORAGE Processor storage temperature -40 85
  • Intel Q6600 | Data Sheet - Page 18
    Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes1, 2 VID Range VID 0.8500 - 1.5 V 3 Processor Number VCC for 775_VR_CONFIG_05 QX6850 3.00 GHz VCC QX6800 2.93 GHz Refer to Table 5 and Figure 1 V 4, 5, 6 QX6700 2.66 GHz Q6700 2.66 GHz Q6600 2.40 GHz
  • Intel Q6600 | Data Sheet - Page 19
    current drawn from VTT plane by only the processor. This specification does not include the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket to determine the total ITT drawn by the
  • Intel Q6600 | Data Sheet - Page 20
    for overshoot allowed as shown in Section 2.5.3. 2. This loadline specification shows the deviation from the VID set point. 3. The processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket
  • Intel Q6600 | Data Sheet - Page 21
    specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands. VCC Overshoot Specifications Symbol Parameter Min Max VID. Die Voltage Validation Overshoot events on processor must meet the specifications in Table 6 when measured across the VCC_SENSE and
  • Intel Q6600 | Data Sheet - Page 22
    (see Table 14 for GTLREF specifications). Termination resistors (RTT) for GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals. FSB
  • Intel Q6600 | Data Sheet - Page 23
    Specifications Table 7. . Table 8. . Table 9. FSB Signal Groups (Sheet 2 of 2) Signal Group Type Signals1 CMOS Open Drain Output Open Drain Input/Output FSB Clock Clock Power In processor systems where no debug port is implemented on the system board, these signals are used to support a
  • Intel Q6600 | Data Sheet - Page 24
    power states. 2.6.3 Table 10. Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications mV. Table 11. Open Drain and TAP Output Signal Group DC Specifications Symbol Parameter Min Max Unit
  • Intel Q6600 | Data Sheet - Page 25
    noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the voltage range at a supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. Refer to Table 4 for VTT specifications. 2. The leakage specification applies to powered
  • Intel Q6600 | Data Sheet - Page 26
    of the GTL+ output driver. 4. COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and COMP8 resistors are to VSS. Clock Specifications 2.7.1 Table 15. Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well
  • Intel Q6600 | Data Sheet - Page 27
    required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. The Intel® Core™2 Extreme Quad-Core processor QX6800, QX6700 and Intel® Core™2 Quad processors Q6600 and Q6700 operate at a 1066 MHz FSB frequency (selected by a 266 MHz
  • Intel Q6600 | Data Sheet - Page 28
    : BCLK[1:0] Rise and Fall Slew Rate 2.5 - 8 V/nS 5 5 T6: Slew Rate Matching N/A N/A 20 % 6 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies based on a 266 MHz BCLK[1:0]. 2. Duty Cycle (High time/Period) must be between 40 and 60
  • Intel Q6600 | Data Sheet - Page 29
    T5: BCLK[1:0] Rise and Fall Slew Rate 2.5 - 8 V/nS 5 6 T6: Slew Rate Matching N/A N/A 20 % 7 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies based on a 333 MHz BCLK[1:0]. 2. Duty Cycle (High time/Period) must be between 40 and 60
  • Intel Q6600 | Data Sheet - Page 30
    4. Differential Clock Crosspoint Specification Crossing Point (mV) 650 600 550 500 550 + 0.5 (VHavg - 700) 450 550 mV 400 300 + 0.5 (VHavg - 700) 350 300 300 mV 250 200 660 670
  • Intel Q6600 | Data Sheet - Page 31
    Package Mechanical Specifications 3 Package Mechanical Specifications Figure 6. The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An
  • Intel Q6600 | Data Sheet - Page 32
    Figure 7. Processor Package Drawing Sheet 1 of 3 Package Mechanical Specifications 32 Datasheet
  • Intel Q6600 | Data Sheet - Page 33
    Package Mechanical Specifications Figure 8. Processor Package Drawing Sheet 2 of 3 Datasheet 33
  • Intel Q6600 | Data Sheet - Page 34
    Figure 9. Processor Package Drawing Sheet 3 of 3 Package Mechanical Specifications 34 Datasheet
  • Intel Q6600 | Data Sheet - Page 35
    . Package Loading Specifications Table 20 provides dynamic and static load specifications for the processor package. These mechanical processor socket. 4. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement. Package Handling Guidelines Table
  • Intel Q6600 | Data Sheet - Page 36
    requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.7 Table 22. Processor Materials Table 22 lists some of
  • Intel Q6600 | Data Sheet - Page 37
    Package Mechanical Specifications Figure 11. Processor Top-Side Markings Example for 1333 MHz Processors INTEL M ©'05 QX6850 INTEL® CORE™2 EXTREME SLxxx [COO] 3.00GHZ/8M/1333/05B [FPO] e4 ATPO S/N Datasheet 37
  • Intel Q6600 | Data Sheet - Page 38
    Package Mechanical Specifications 3.9 Processor Land Coordinates . Figure 12. Figure 12 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Processor Land Coordinates and Quadrants (Top View) V /V CC SS 30 29
  • Intel Q6600 | Data Sheet - Page 39
    by land number and they show the physical location of each signal on the package land array (top view). Table 23 is a listing of all processor lands ordered alphabetically by land (signal) name. Table 24 is also a listing of all processor lands; the ordering is by land number. Datasheet 39
  • Intel Q6600 | Data Sheet - Page 40
    Land Listing and Signal Descriptions Figure 13. land-out Diagram (Top View - Left Side) 30 29 28 AN VCC VCC VSS 27 VSS 26 25 24 23 22 21 20 VCC VCC VSS VSS VCC VCC VSS AM VCC AL VCC AK VSS AJ VSS AH VCC AG VCC AF VSS AE VSS AD VCC AC VCC AB VSS VCC VCC VSS VSS VCC VCC VSS VSS VCC
  • Intel Q6600 | Data Sheet - Page 41
    Land Listing and Signal Descriptions Figure 14. 14 13 VCC VSS VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VSS land-out Diagram (Top View - Right Side) 12 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS 11 10 VCC VSS VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS
  • Intel Q6600 | Data Sheet - Page 42
    Input G28 Clock Input Table 23. Alphabetical Land Assignments Land Name Land # Signal Buffer Type Direction BNR# BPM0# Power/Other Output H30 Power/Other Output G30 Power/Other Output A13 Power/Other Input T1 Power/Other Input G2 Power/Other Input R1 Power/Other Input B13 Power
  • Intel Q6600 | Data Sheet - Page 43
    Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Table 23. Alphabetical Land Assignments Land Name Land # Signal Buffer Type Direction D57# D58# D59# D60# D61# D62# D63# DBI0# DBI1# DBI2# DBI3# DBR# DBSY# DEFER# DRDY# DSTBN0
  • Intel Q6600 | Data Sheet - Page 44
    Signal Descriptions Table 23. Alphabetical Land Assignments Land Name Land # Signal Buffer Type Direction FC32 H15 Power/Other FC33 H16 Power/Other FC34 J17 Power/Other FC35 H4 Power/Other FC36 AD3 Power/Other FC37 AB3 Power/Other FC39 AA2 Power/Other FC4 T2 Power/Other FC40
  • Intel Q6600 | Data Sheet - Page 45
    AE21 Power/Other AE22 Power/Other AE23 Power/Other AE9 Power/Other AF11 Power/Other AF12 Power/Other AF14 Power/Other AF15 Power/Other AF18 Power/Other AF19 Power/Other AF21 Power/Other Input Input Table 23. Alphabetical Land Assignments Land Name Land # Signal Buffer Type Direction
  • Intel Q6600 | Data Sheet - Page 46
    AL21 Power/Other AL22 Power/Other AL25 Power/Other AL26 Power/Other AL29 Power/Other AL30 Power/Other AL8 Power/Other AL9 Power/Other AM11 Power/Other AM12 Power/Other AM14 Power/Other AM15 Power/Other AM18 Power/Other Table 23. Alphabetical Land Assignments Land Name Land # Signal Buffer Type
  • Intel Q6600 | Data Sheet - Page 47
    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Table 23. Alphabetical Land Assignments Land Name Land # Signal Buffer Type
  • Intel Q6600 | Data Sheet - Page 48
    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Output Output Output Output Output Table 23. Alphabetical Land Assignments Land Name Land # Signal Buffer Type
  • Intel Q6600 | Data Sheet - Page 49
    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Table 23. Alphabetical Land Assignments Land Name Land # Signal Buffer Type
  • Intel Q6600 | Data Sheet - Page 50
    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Table 23. Alphabetical Land Assignments Land Name Land # Signal Buffer Type
  • Intel Q6600 | Data Sheet - Page 51
    T6 Power/Other T7 Power/Other U7 Power/Other V23 Power/Other V24 Power/Other V25 Power/Other V26 Power/Other V27 Power/Other V28 Power/Other V29 Power/Other V3 Power/Other V30 Power/Other V6 Power/Other V7 Power/Other Table 23. Alphabetical Land Assignments Land Name Land # Signal Buffer Type
  • Intel Q6600 | Data Sheet - Page 52
    Source Synch Input/Output Source Synch Input/Output Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction B11 VSS Power/Other B12 D13# Source Synch Input/Output B13 COMP8 Power/Other Input B14 VSS Power/Other B15 D53# Source Synch Input/Output B16
  • Intel Q6600 | Data Sheet - Page 53
    /Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction D29 D30 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11
  • Intel Q6600 | Data Sheet - Page 54
    Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction F11 D23# Source Synch Input/Output F12 D24# Source Synch Input/Output F13 VSS Power/Other F14 D28# Source Synch Input/Output F15 D30# Source Synch Input/Output
  • Intel Q6600 | Data Sheet - Page 55
    A20M# Asynch CMOS Input K4 REQ0# Source Synch Input/Output K5 VSS Power/Other K6 REQ3# Source Synch Input/Output K7 VSS Power/Other K8 VCC Power/Other Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction K23 K24 K25 K26 K27 K28 K29 K30 L1 L2 L3 L4
  • Intel Q6600 | Data Sheet - Page 56
    # Source Synch Input/Output VSS Power/Other ADSTB0# Source Synch Input/Output Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction R7 VSS Power/Other R8 VCC Power/Other R23 VSS Power/Other R24 VSS Power/Other R25 VSS Power/Other R26 R27 R28 R29
  • Intel Q6600 | Data Sheet - Page 57
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction Y5 Y6 Y7 Y8 Y23 Y24
  • Intel Q6600 | Data Sheet - Page 58
    Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Input Power/Other Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction AE3 FC18 Power/Other AE4 RESERVED
  • Intel Q6600 | Data Sheet - Page 59
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction AG21 AG22 AG23 AG24 AG25 AG26 AG27
  • Intel Q6600 | Data Sheet - Page 60
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Input Power/Other Output Power/Other Power/Other Power/Other Power/Other Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type
  • Intel Q6600 | Data Sheet - Page 61
    Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Output Output Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type
  • Intel Q6600 | Data Sheet - Page 62
    -byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB. A[35:3]# are
  • Intel Q6600 | Data Sheet - Page 63
    Descriptions Table 25. Signal Description (Sheet 2 of 9) Name Type Description BPM[5:0]# BPMb[3:0]# BPRI# BR0# BSEL[2:0] COMP8 COMP[3:0] Input/ Output BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which
  • Intel Q6600 | Data Sheet - Page 64
    and Signal Descriptions Table 25. Signal Description (Sheet 3 of 9) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY
  • Intel Q6600 | Data Sheet - Page 65
    event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. Input GTLREF[3:0] determine the
  • Intel Q6600 | Data Sheet - Page 66
    and continue to execute noncontrol floatingpoint instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set
  • Intel Q6600 | Data Sheet - Page 67
    of the processor FSB throughout the bus locked operation and ensure the atomicity of lock. Input/ PECI is a proprietary one-wire bus interface. See Section 5.3 for Output details. Input/ Output As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor
  • Intel Q6600 | Data Sheet - Page 68
    Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 7 of 9) Name Type Description RS[2:0]# SKTOCC# SMI# STPCLK# TCK specification support. TDO connects to core 1. TDO_M connects to core 0. Input TESTHI[13,11:10,7:0] must be connected to the processor's appropriate power
  • Intel Q6600 | Data Sheet - Page 69
    attempt to reduce the processor junction temperature. To protect the processor, its core voltage (VCC) must supply for the VID signals becomes valid. The VID signals are needed to support the processor voltage specification variations. See Table 2 for definitions of these signals. The VR must supply
  • Intel Q6600 | Data Sheet - Page 70
    V27 as described in the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. Miscellaneous voltage supply. The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a voltage supply for some signals that require termination to VTT on the
  • Intel Q6600 | Data Sheet - Page 71
    reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (TC) specifications when operating at or below the Thermal Design Power (TDP) value listed per frequency in Table 26
  • Intel Q6600 | Data Sheet - Page 72
    are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 26 instead of the maximum processor power consumption. The Thermal Monitor feature is
  • Intel Q6600 | Data Sheet - Page 73
    Thermal Specifications and Design Considerations Table 27. Thermal Profile for 130 W Processors Power (W) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Maximum Tc (°C) 42.4 42.7 43.1 43.4 43.8 44.1 44.4 44.8 45.1 45.5 45.8 46.1 46.5 46.8 47.2 47.5 47.8 Power (W) 34 36 38 40 42 44 46 48 50 52 54
  • Intel Q6600 | Data Sheet - Page 74
    Thermal Specifications and Design Considerations Table 28. Thermal Profile for 105 W Processors Power Maximum (W) Tc (°C) Power Maximum (W) Tc (°C) 0 43.3 2 43 51.2 46 51.6 48 51.9 50 52.3 52 52.7 54 53.0 Power (W) 56 58 60 62 64 66 68 70 72 74 76 78 80 82 Maximum Tc (°C) 53.4
  • Intel Q6600 | Data Sheet - Page 75
    Thermal Specifications and Design Considerations Table 29. Thermal Profile 95 W Processors Power Maximum (W) Tc (°C) Power Maximum (W) Tc (°C) 0 44.4 2 45.0 4 45.5 6 46.1 8 46.6 10 47.2 12 47.8 14 48.3 16 48.9 18 49.4 20 50.0 22 50.6 24 51.1 26 51.7
  • Intel Q6600 | Data Sheet - Page 76
    reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications. The temperature at which Thermal
  • Intel Q6600 | Data Sheet - Page 77
    drivers, or interrupt handling routines. Thermal Monitor 2 The processor also supports an additional power reduction capability known as Thermal Monitor 2. This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor
  • Intel Q6600 | Data Sheet - Page 78
    this mechanism to limit the processor temperature. If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a '1', the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand
  • Intel Q6600 | Data Sheet - Page 79
    when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 25). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 25. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles
  • Intel Q6600 | Data Sheet - Page 80
    Specifications and Design Considerations 5.3 Platform Environment Control Interface (PECI) 5.3.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset TCC Activation Temperature Fan Speed (RPM) Min PECI = -20 Max PECI = -10 PECI = 0 Temperature Note: Not
  • Intel Q6600 | Data Sheet - Page 81
    Code Support The error codes supported for the processor GetTemp0() and GetTemp1() commands are listed in Table 30. GetTemp0() and GetTemp1() Error Codes Error Code Description 8000h 8002h General sensor error Sensor is operational, but has detected a temperature below its operational range
  • Intel Q6600 | Data Sheet - Page 82
    Thermal Specifications and Design Considerations 82 Datasheet
  • Intel Q6600 | Data Sheet - Page 83
    by configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the package. 6.2 Clock Control and Low Power States The processor allows the use of AutoHALT and Stop Grant states to reduce power consumption by stopping the clock
  • Intel Q6600 | Data Sheet - Page 84
    for details about the HALT and Extended HALT states. HALT Powerdown State HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted, however, the other
  • Intel Q6600 | Data Sheet - Page 85
    of supporting Extended HALT State. More details on which processor frequencies will support this feature will be provided in future releases of the Intel® Core™2 Extreme Quad-Core Processor QX6700 and Intel® Core™2 Quad Processor Q6000 Sequence Specification Update when available. The processor will
  • Intel Q6600 | Data Sheet - Page 86
    state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB). After the snoop is serviced, the processor will return to the Stop Grant state or HALT Power Down state, as appropriate. Extended HALT Snoop State The Extended HALT Snoop State is the default
  • Intel Q6600 | Data Sheet - Page 87
    Boxed Processor Specifications 7 Boxed Processor Specifications The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling
  • Intel Q6600 | Data Sheet - Page 88
    Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 22 shows a mechanical representation of the boxed processor. Figure 23. Clearance is required around the fan
  • Intel Q6600 | Data Sheet - Page 89
    Boxed Processor Specifications Figure 24. Space Requirements for the Boxed Processor (Top View) Figure 25. NOTES: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Space Requirements for the Boxed Processor (Overall View)
  • Intel Q6600 | Data Sheet - Page 90
    V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 26. Baseboards must provide a matched power header to support the boxed processor. Table 32 contains specifications
  • Intel Q6600 | Data Sheet - Page 91
    Processor Specifications Figure 26. Boxed Processor Fan Heatsink Power Table 32. Fan Heatsink Power and Signal Specifications Description Min Typ +12 V: 12 volt fan power supply 2. Open drain type, pulse width modulated. 3. Fan will have pull-up resistor to 4.75 V maximum of 5.25 V. Max 12.6 - -
  • Intel Q6600 | Data Sheet - Page 92
    system, and ultimately the responsibility of the system integrator. The processor temperature specification is in Chapter 5. The boxed processor fan heatsink is able to keep the processor temperature within the specifications (see Table 26) in chassis that provide good thermal management. For the
  • Intel Q6600 | Data Sheet - Page 93
    Boxed Processor Specifications Figure 28. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View) Figure 29. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View) Datasheet 93
  • Intel Q6600 | Data Sheet - Page 94
    system integrator. The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of the fan for the boxed processor. See Table 32 for specific requirements. Fan Speed Control Operation (Intel® Core™2 Quad processor) If the boxed processor fan heatsink 4-pin
  • Intel Q6600 | Data Sheet - Page 95
    Set Point Lowest Noise Level X Y Z Internal Chassis Temperature (Degrees C) Table 33. Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point (ºC) Boxed Processor Fan Speed Notes X ≤ 30 When the internal chassis temperature is below or equal to this set point
  • Intel Q6600 | Data Sheet - Page 96
    . Under thermistor controlled mode, the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet. For more details on specific motherboard requirements for 4-wire based fan speed control refer to the appropriate Thermal and Mechanical Design
  • Intel Q6600 | Data Sheet - Page 97
    the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing a r system that can make use of an LAI: mechanical and electrical. Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI lands plug into
  • Intel Q6600 | Data Sheet - Page 98
    Debug Tools Specifications 98 Datasheet
  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
Document Number: 315592-005
Intel
®
Core™2 Extreme Quad-Core
Processor QX6000
Δ
Sequence and
Intel
®
Core™2 Quad Processor
Q6000
Δ
Sequence
Datasheet
—on 65 nm Process in the 775-land LGA Package supporting
Intel
®
64
architecture and Intel
®
Virtualization Technology
±
August 2007