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Intel Q6600 Data Sheet - Page 26

Clock Specifications - driver

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Electrical Specifications 2.6.3.1 Table 14. 2.7 GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 8 for details on which GTL+ signals do not include on-die termination. Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 14 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits. GTL+ Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes1 GTLREF_PU GTLREF pull-up resistor 124 * 0.99 124 124 * 1.01 Ω 2 GTLREF_PD GTLREF pull-down resistor 210 * 0.99 210 210 * 1.01 Ω 2 RTT COMP[3:0] Termination Resistance COMP Resistance 45 50 55 Ω 3 49.40 49.90 50.40 Ω 4 COMP8 COMP Resistance 24.65 24.90 25.15 Ω 4 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each GTLEREF land). Refer to the applicable platform design guide for implementation details. 3. RTT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver. 4. COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and COMP8 resistors are to VSS. Clock Specifications 2.7.1 Table 15. Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor's core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative. Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB Frequency Core Frequency (266 MHz BCLK/ 1066 MHz FSB) Core Frequency (333 MHz BCLK/ 1333 MHz FSB) Notes1, 2 1/6 1.60 GHz 2.00 GHz - 1/7 1.87 GHz 2.33 GHz - 1/8 2.13 GHz 2.66 GHz - 1/9 2.40 GHz 3.00 GHz - 1/10 2.66 GHz 3.33 GHz - 1/11 2.93 GHz 3.66 GHz - 1/12 3.20 GHz 4.00 GHz - NOTES: 1. Individual processors operate only at or below the rated frequency. 2. Listed frequencies are not necessarily committed production frequencies. 26 Datasheet

Section	Page
Contents	3
Figures	5
Tables	6
Revision History	7
Intel® Core™2 Extreme Quad-Core Processor QX6000 and Intel® Core™2 Quad Processor Q6000 Sequence Features	8
1 Introduction	9
1.1 Terminology	9
1.1.1 Processor Terminology	10
1.2 References	11
Table 1. References	11
2 Electrical Specifications	13
2.1 Power and Ground Lands	13
2.2 Decoupling Guidelines	13
2.2.1 VCC Decoupling	13
2.2.2 VTT Decoupling	13
2.2.3 FSB Decoupling	14
2.3 Voltage Identification	14
Table 2. Voltage Identification Definition	15
2.4 Reserved, Unused, and TESTHI Signals	16
2.5 Voltage and Current Specification	17
2.5.1 Absolute Maximum and Minimum Ratings	17
Table 3. Absolute Maximum and Minimum Ratings	17
2.5.2 DC Voltage and Current Specification	18
Table 4. Voltage and Current Specifications	18
Table 5. VCC Static and Transient Tolerance	19
Figure 1. VCC Static and Transient Tolerance	20
2.5.3 VCC Overshoot	21
Table 6. VCC Overshoot Specifications	21
Figure 2. VCC Overshoot Example Waveform	21
2.5.4 Die Voltage Validation	21
2.6 Signaling Specifications	22
2.6.1 FSB Signal Groups	22
Table 7. FSB Signal Groups (Sheet 1 of 2)	22
Table 8. Signal Characteristics	23
Table 9. Signal Reference Voltages	23
2.6.2 CMOS and Open Drain Signals	24
2.6.3 Processor DC Specifications	24
Table 10. GTL+ Signal Group DC Specifications	24
Table 11. Open Drain and TAP Output Signal Group DC Specifications	24
Table 12. CMOS Signal Group DC Specifications	25
Table 13. PECI DC Electrical Limits	25
2.6.3.1 GTL+ Front Side Bus Specifications	26
Table 14. GTL+ Bus Voltage Definitions	26
2.7 Clock Specifications	26
2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	26
Table 15. Core Frequency to FSB Multiplier Configuration	26
2.7.2 FSB Frequency Select Signals (BSEL[2:0])	27
Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]	27
2.7.3 Phase Lock Loop (PLL) and Filter	27
2.7.4 BCLK[1:0] Specifications	28
Table 17. Front Side Bus Differential BCLK Specifications	28
Table 18. FSB Differential Clock Specifications (1066 MHz FSB)	28
Table 19. FSB Differential Clock Specifications (1333 MHz FSB)	29
Figure 3. Differential Clock Waveform	29
Figure 4. Differential Clock Crosspoint Specification	30
Figure 5. Differential Measurements	30
3 Package Mechanical Specifications	31
Figure 6. Processor Package Assembly Sketch	31
3.1 Package Mechanical Drawing	31
Figure 7. Processor Package Drawing Sheet 1 of 3	32
Figure 8. Processor Package Drawing Sheet 2 of 3	33
Figure 9. Processor Package Drawing Sheet 3 of 3	34
3.2 Processor Component Keep-Out Zones	35
3.3 Package Loading Specifications	35
Table 20. Processor Loading Specifications	35
3.4 Package Handling Guidelines	35
Table 21. Package Handling Guidelines	35
3.5 Package Insertion Specifications	36
3.6 Processor Mass Specification	36
3.7 Processor Materials	36
Table 22. Processor Materials	36
3.8 Processor Markings	36
Figure 10. Processor Top-Side Markings Example for 1066 MHz Processors	36
Figure 11. Processor Top-Side Markings Example for 1333 MHz Processors	37
3.9 Processor Land Coordinates	38
Figure 12. Processor Land Coordinates and Quadrants (Top View)	38
4 Land Listing and Signal Descriptions	39
4.1 Processor Land Assignments	39
Figure 13. land-out Diagram (Top View - Left Side)	40
Figure 14. land-out Diagram (Top View - Right Side)	41
Table 23. Alphabetical Land Assignments	42
Table 24. Numerical Land Assignment	52
4.2 Alphabetical Signals Reference	62
Table 25. Signal Description (Sheet 1 of 9)	62
5 Thermal Specifications and Design Considerations	71
5.1 Processor Thermal Specifications	71
5.1.1 Thermal Specifications	71
Table 26. Processor Thermal Specifications	72
Table 27. Thermal Profile for 130 W Processors	73
Figure 15. Thermal Profile for 130 W Processors	73
Table 28. Thermal Profile for 105 W Processors	74
Figure 16. Thermal Profile for 105 W Processors	74
Table 29. Thermal Profile 95 W Processors	75
Figure 17. Thermal Profile 95 W Processors	75
5.1.2 Thermal Metrology	76
Figure 18. Case Temperature (TC) Measurement Location	76
5.2 Processor Thermal Features	76
5.2.1 Thermal Monitor	76
5.2.2 Thermal Monitor 2	77
Figure 19. Thermal Monitor 2 Frequency and Voltage Ordering	78
5.2.3 On-Demand Mode	78
5.2.4 PROCHOT# Signal	79
5.2.5 THERMTRIP# Signal	79
5.3 Platform Environment Control Interface (PECI)	80
5.3.1 Introduction	80
5.3.1.1 TCONTROL and TCC Activation on PECI-Based Systems	80
Figure 20. Conceptual Fan Control on PECI-Based Platforms	80
5.3.2 PECI Specifications	81
5.3.2.1 PECI Device Address	81
5.3.2.2 PECI Command Support	81
5.3.2.3 PECI Fault Handling Requirements	81
5.3.2.4 PECI GetTemp0() and GetTemp1() Error Code Support	81
Table 30. GetTemp0() and GetTemp1() Error Codes	81
6 Features	83
6.1 Power-On Configuration Options	83
Table 31. Power-On Configuration Option Signals	83
6.2 Clock Control and Low Power States	83
Figure 21. Processor Low Power State Machine	84
6.2.1 Normal State	84
6.2.2 HALT and Extended HALT Powerdown States	84
6.2.2.1 HALT Powerdown State	84
6.2.2.2 Extended HALT Powerdown State	85
6.2.3 Stop Grant State	85
6.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	86
6.2.4.1 HALT Snoop State, Stop Grant Snoop State	86
6.2.4.2 Extended HALT Snoop State	86
7 Boxed Processor Specifications	87
Figure 22. Mechanical Representation of the Boxed Processor	87
7.1 Mechanical Specifications	88
7.1.1 Boxed Processor Cooling Solution Dimensions	88
Figure 23. Space Requirements for the Boxed Processor (Side View)	88
Figure 24. Space Requirements for the Boxed Processor (Top View)	89
Figure 25. Space Requirements for the Boxed Processor (Overall View)	89
7.1.2 Boxed Processor Fan Heatsink Weight	90
7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	90
7.2 Electrical Requirements	90
7.2.1 Fan Heatsink Power Supply	90
Figure 26. Boxed Processor Fan Heatsink Power Cable Connector Description	91
Table 32. Fan Heatsink Power and Signal Specifications	91
Figure 27. Baseboard Power Header Placement Relative to Processor Socket	92
7.3 Thermal Specifications	92
7.3.1 Boxed Processor Cooling Requirements	92
Figure 28. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View)	93
Figure 29. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)	93
7.3.2 Fan Speed Control Operation (Intel® Core™2 Extreme processors only)	94
7.3.3 Fan Speed Control Operation (Intel® Core™2 Quad processor)	94
Figure 30. Boxed Processor Fan Heatsink Set Points	95
Table 33. Fan Heatsink Power and Signal Specifications	95
8 Debug Tools Specifications	97
8.1 Logic Analyzer Interface (LAI)	97
8.1.1 Mechanical Considerations	97

Match case Limit results 1 per page

Electrical Specifications

Datasheet

2.6.3.1

GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the

processor silicon. See

Table 8

for details on which GTL+ signals do not include on-die

termination.

Valid high and low levels are determined by the input buffers by comparing with a

reference voltage called GTLREF.

Table 14

lists the GTLREF specifications. The GTL+

reference voltage (GTLREF) should be generated on the system board using high

precision voltage divider circuits.

2.7

Clock Specifications

2.7.1

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous generation processors, the processor’s core frequency is a

multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its

default ratio during manufacturing.

The processor uses a differential clocking implementation. For more information on the

processor clocking, contact your Intel field representative.

Table 14.

GTL+ Bus Voltage Definitions

Symbol

Parameter

Min

Typ

Max

Units

Notes

NOTES:

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

GTLREF_PU

GTLREF pull-up resistor

124 * 0.99

124

124 * 1.01

GTLREF is to be generated from V

by a voltage divider of 1% resistors (one divider for each

GTLEREF land). Refer to the

applicable platform design guide

for implementation details.

GTLREF_PD

GTLREF pull-down resistor

210 * 0.99

210

210 * 1.01

Termination Resistance

is the on-die termination resistance measured at V

/3 of the GTL+ output driver.

COMP[3:0]

COMP Resistance

49.40

49.90

50.40

COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and

COMP8 resistors are to V

COMP8

COMP Resistance

24.65

24.90

25.15

Table 15.

Core Frequency to FSB Multiplier Configuration

Multiplication of System

Core Frequency to FSB

Frequency

Core Frequency

(266 MHz BCLK/

1066 MHz FSB)

Core Frequency

(333 MHz BCLK/

1333 MHz FSB)

Notes

1, 2

NOTES:

Individual processors operate only at or below the rated frequency.

Listed frequencies are not necessarily committed production frequencies.

1/6

1.60 GHz

2.00 GHz

1/7

1.87 GHz

2.33 GHz

1/8

2.13 GHz

2.66 GHz

1/9

2.40 GHz

3.00 GHz

1/10

2.66 GHz

3.33 GHz

1/11

2.93 GHz

3.66 GHz

1/12

3.20 GHz

4.00 GHz