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Intel Q6600 Data Sheet - Page 22

Signaling Specifications - power supply

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Electrical Specifications 2.6 2.6.1 Table 7. Signaling Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as VTT. Because platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families. The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see Table 14 for GTLREF specifications). Termination resistors (RTT) for GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals. FSB Signal Groups The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF[3:0] as a reference level. In this document, the term "GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, "GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 7 identifies which signals are common clock, source synchronous, and asynchronous. FSB Signal Groups (Sheet 1 of 2) Signal Group Type Signals1 GTL+ Common Clock Input GTL+ Common Clock I/O Synchronous to BCLK[1:0] Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY# ADS#, BNR#, BPM[5:0]#, BPMb[3:0]#, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK# GTL+ Source Synchronous to Synchronous I/O assoc. strobe Signals REQ[4:0]#, A[16:3]#3 A[35:17]#3 D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# Associated Strobe ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3# GTL+ Strobes Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# 22 Datasheet

Section	Page
Contents	3
Figures	5
Tables	6
Revision History	7
Intel® Core™2 Extreme Quad-Core Processor QX6000 and Intel® Core™2 Quad Processor Q6000 Sequence Features	8
1 Introduction	9
1.1 Terminology	9
1.1.1 Processor Terminology	10
1.2 References	11
Table 1. References	11
2 Electrical Specifications	13
2.1 Power and Ground Lands	13
2.2 Decoupling Guidelines	13
2.2.1 VCC Decoupling	13
2.2.2 VTT Decoupling	13
2.2.3 FSB Decoupling	14
2.3 Voltage Identification	14
Table 2. Voltage Identification Definition	15
2.4 Reserved, Unused, and TESTHI Signals	16
2.5 Voltage and Current Specification	17
2.5.1 Absolute Maximum and Minimum Ratings	17
Table 3. Absolute Maximum and Minimum Ratings	17
2.5.2 DC Voltage and Current Specification	18
Table 4. Voltage and Current Specifications	18
Table 5. VCC Static and Transient Tolerance	19
Figure 1. VCC Static and Transient Tolerance	20
2.5.3 VCC Overshoot	21
Table 6. VCC Overshoot Specifications	21
Figure 2. VCC Overshoot Example Waveform	21
2.5.4 Die Voltage Validation	21
2.6 Signaling Specifications	22
2.6.1 FSB Signal Groups	22
Table 7. FSB Signal Groups (Sheet 1 of 2)	22
Table 8. Signal Characteristics	23
Table 9. Signal Reference Voltages	23
2.6.2 CMOS and Open Drain Signals	24
2.6.3 Processor DC Specifications	24
Table 10. GTL+ Signal Group DC Specifications	24
Table 11. Open Drain and TAP Output Signal Group DC Specifications	24
Table 12. CMOS Signal Group DC Specifications	25
Table 13. PECI DC Electrical Limits	25
2.6.3.1 GTL+ Front Side Bus Specifications	26
Table 14. GTL+ Bus Voltage Definitions	26
2.7 Clock Specifications	26
2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	26
Table 15. Core Frequency to FSB Multiplier Configuration	26
2.7.2 FSB Frequency Select Signals (BSEL[2:0])	27
Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]	27
2.7.3 Phase Lock Loop (PLL) and Filter	27
2.7.4 BCLK[1:0] Specifications	28
Table 17. Front Side Bus Differential BCLK Specifications	28
Table 18. FSB Differential Clock Specifications (1066 MHz FSB)	28
Table 19. FSB Differential Clock Specifications (1333 MHz FSB)	29
Figure 3. Differential Clock Waveform	29
Figure 4. Differential Clock Crosspoint Specification	30
Figure 5. Differential Measurements	30
3 Package Mechanical Specifications	31
Figure 6. Processor Package Assembly Sketch	31
3.1 Package Mechanical Drawing	31
Figure 7. Processor Package Drawing Sheet 1 of 3	32
Figure 8. Processor Package Drawing Sheet 2 of 3	33
Figure 9. Processor Package Drawing Sheet 3 of 3	34
3.2 Processor Component Keep-Out Zones	35
3.3 Package Loading Specifications	35
Table 20. Processor Loading Specifications	35
3.4 Package Handling Guidelines	35
Table 21. Package Handling Guidelines	35
3.5 Package Insertion Specifications	36
3.6 Processor Mass Specification	36
3.7 Processor Materials	36
Table 22. Processor Materials	36
3.8 Processor Markings	36
Figure 10. Processor Top-Side Markings Example for 1066 MHz Processors	36
Figure 11. Processor Top-Side Markings Example for 1333 MHz Processors	37
3.9 Processor Land Coordinates	38
Figure 12. Processor Land Coordinates and Quadrants (Top View)	38
4 Land Listing and Signal Descriptions	39
4.1 Processor Land Assignments	39
Figure 13. land-out Diagram (Top View - Left Side)	40
Figure 14. land-out Diagram (Top View - Right Side)	41
Table 23. Alphabetical Land Assignments	42
Table 24. Numerical Land Assignment	52
4.2 Alphabetical Signals Reference	62
Table 25. Signal Description (Sheet 1 of 9)	62
5 Thermal Specifications and Design Considerations	71
5.1 Processor Thermal Specifications	71
5.1.1 Thermal Specifications	71
Table 26. Processor Thermal Specifications	72
Table 27. Thermal Profile for 130 W Processors	73
Figure 15. Thermal Profile for 130 W Processors	73
Table 28. Thermal Profile for 105 W Processors	74
Figure 16. Thermal Profile for 105 W Processors	74
Table 29. Thermal Profile 95 W Processors	75
Figure 17. Thermal Profile 95 W Processors	75
5.1.2 Thermal Metrology	76
Figure 18. Case Temperature (TC) Measurement Location	76
5.2 Processor Thermal Features	76
5.2.1 Thermal Monitor	76
5.2.2 Thermal Monitor 2	77
Figure 19. Thermal Monitor 2 Frequency and Voltage Ordering	78
5.2.3 On-Demand Mode	78
5.2.4 PROCHOT# Signal	79
5.2.5 THERMTRIP# Signal	79
5.3 Platform Environment Control Interface (PECI)	80
5.3.1 Introduction	80
5.3.1.1 TCONTROL and TCC Activation on PECI-Based Systems	80
Figure 20. Conceptual Fan Control on PECI-Based Platforms	80
5.3.2 PECI Specifications	81
5.3.2.1 PECI Device Address	81
5.3.2.2 PECI Command Support	81
5.3.2.3 PECI Fault Handling Requirements	81
5.3.2.4 PECI GetTemp0() and GetTemp1() Error Code Support	81
Table 30. GetTemp0() and GetTemp1() Error Codes	81
6 Features	83
6.1 Power-On Configuration Options	83
Table 31. Power-On Configuration Option Signals	83
6.2 Clock Control and Low Power States	83
Figure 21. Processor Low Power State Machine	84
6.2.1 Normal State	84
6.2.2 HALT and Extended HALT Powerdown States	84
6.2.2.1 HALT Powerdown State	84
6.2.2.2 Extended HALT Powerdown State	85
6.2.3 Stop Grant State	85
6.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State	86
6.2.4.1 HALT Snoop State, Stop Grant Snoop State	86
6.2.4.2 Extended HALT Snoop State	86
7 Boxed Processor Specifications	87
Figure 22. Mechanical Representation of the Boxed Processor	87
7.1 Mechanical Specifications	88
7.1.1 Boxed Processor Cooling Solution Dimensions	88
Figure 23. Space Requirements for the Boxed Processor (Side View)	88
Figure 24. Space Requirements for the Boxed Processor (Top View)	89
Figure 25. Space Requirements for the Boxed Processor (Overall View)	89
7.1.2 Boxed Processor Fan Heatsink Weight	90
7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	90
7.2 Electrical Requirements	90
7.2.1 Fan Heatsink Power Supply	90
Figure 26. Boxed Processor Fan Heatsink Power Cable Connector Description	91
Table 32. Fan Heatsink Power and Signal Specifications	91
Figure 27. Baseboard Power Header Placement Relative to Processor Socket	92
7.3 Thermal Specifications	92
7.3.1 Boxed Processor Cooling Requirements	92
Figure 28. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View)	93
Figure 29. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)	93
7.3.2 Fan Speed Control Operation (Intel® Core™2 Extreme processors only)	94
7.3.3 Fan Speed Control Operation (Intel® Core™2 Quad processor)	94
Figure 30. Boxed Processor Fan Heatsink Set Points	95
Table 33. Fan Heatsink Power and Signal Specifications	95
8 Debug Tools Specifications	97
8.1 Logic Analyzer Interface (LAI)	97
8.1.1 Mechanical Considerations	97

Match case Limit results 1 per page

Electrical Specifications

Datasheet

2.6

Signaling Specifications

Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling

technology. This technology provides improved noise margins and reduced ringing

through low voltage swings and controlled edge rates. Platforms implement a

termination voltage level for GTL+ signals defined as V

. Because platforms implement

separate power planes for each processor (and chipset), separate V

and V

supplies

are necessary. This configuration allows for improved noise tolerance as processor

frequency increases. Speed enhancements to data and address busses have caused

signal integrity considerations and platform design methods to become even more

critical than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to

determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the

motherboard (see

Table 14

for GTLREF specifications). Termination resistors (R

) for

GTL+ signals are provided on the processor silicon and are terminated to V

. Intel

chipsets will also provide on-die termination, thus eliminating the need to terminate the

bus on the motherboard for most GTL+ signals.

2.6.1

FSB Signal Groups

The front side bus signals have been combined into groups by buffer type. GTL+ input

signals have differential input buffers, which use GTLREF[3:0] as a reference level. In

this document, the term “GTL+ Input” refers to the GTL+ input group as well as the

GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output

group as well as the GTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify

two sets of timing parameters. One set is for common clock signals which are

dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second

set is for the source synchronous signals which are relative to their respective strobe

lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are

still present (A20M#, IGNNE#, etc.) and can become active at any time during the

clock cycle.

Table 7

identifies which signals are common clock, source synchronous,

and asynchronous.

Table 7.

FSB Signal Groups (Sheet 1 of 2)

Signal Group

Type

Signals

GTL+ Common

Clock Input

Synchronous to

BCLK[1:0]

BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#

GTL+ Common

Clock I/O

Synchronous to

BCLK[1:0]

ADS#, BNR#, BPM[5:0]#, BPMb[3:0]#, BR0#, DBSY#,

DRDY#, HIT#, HITM#, LOCK#

GTL+ Source

Synchronous I/O

Synchronous to

assoc. strobe

GTL+ Strobes

Synchronous to

BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

Signals

Associated Strobe

REQ[4:0]#, A[16:3]#

ADSTB0#

A[35:17]#

ADSTB1#

D[15:0]#, DBI0#

DSTBP0#, DSTBN0#

D[31:16]#, DBI1#

DSTBP1#, DSTBN1#

D[47:32]#, DBI2#

DSTBP2#, DSTBN2#

D[63:48]#, DBI3#

DSTBP3#, DSTBN3#