Intel SL6VU Specification Update - Page 10

Summary Tables of Changes R NO. E0 nC1 nD1 Plans ERRATA AC3 X AC4 X X AC5 X X AC6 X X AC7 X X AC8 X X AC9 X X AC10 X AC11 X X AC12 X AC13 X AC14 X AC15 X X AC16 X X AC17 X AC18 X X AC19 X AC20 X X AC21 X AC22 X AC23 X X AC24 X X AC25 X AC26 X AC27 X X Fixed Uncacheable (UC) code in same line as write back (WB) data may lead to data corruption X NoFix Transaction is not retried after BINIT# X NoFix Invalid opcode 0FFFh requires a ModRM byte X NoFix FSW may not be completely restored after page fault on FRSTOR or FLDENV instructions X NoFix The processor flags #PF instead of #AC on an unlocked CMPXCHG8B instruction X NoFix When in no-fill mode the memory type of large pages are incorrectly forced to uncacheable X NoFix Processor may hang due to speculative page walks to nonexistent system memory Fixed Writing a performance counter may result in incorrect value X NoFix IA32_MC0_STATUS register overflow bit not set correctly Fixed Performance counter may contain incorrect value after being stopped NoFix MCA error code field in IA32_MC0_STATUS register may become out of sync with the rest of the register NoFix The IA32_MC1_STATUS register may contain incorrect information for correctable errors X NoFix Debug mechanisms may not function as expected X NoFix Machine check architecture error reporting and recovery may not work as expected Fixed Processor may timeout waiting for a device to respond after ~0.67 seconds X NoFix Cascading of performance counters does not work correctly when forced overflow is enabled Fixed IA32_MC1_STATUS MSR ADDRESS VALID bit may be set when no valid address is available X NoFix EMON event counting of x87 loads may not work as expected Fixed Software controlled clock modulation using a 12.5% or 25% duty cycle may cause the processor to hang Fixed SQRTPD and SQRTSD may return QnaN indefinite instead of negative zero X PlanFix Bus Invalidate Line requests that return unexpected data may result in L1 cache corruption X PlanFix Write Combining (WC) load may result in unintended address on system bus Fixed Incorrect data may be returned when page tables are in Write Combining (WC) memory space PlanFix Buffer on resistance may exceed specification X NoFix Processor issues inconsistent transaction size attributes for locked operation 10 Intel® Celeron® Processor in the 478-Pin Package Specification Update