Intel SL6VU Specification Update - Page 33

AC36., L2 Cache May Contain Stale Data in the Exclusive State, AC37., Fetch

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Errata R AC36. L2 Cache May Contain Stale Data in the Exclusive State Problem: If a cacheline (A) is in Modified (M) state in the write-combining (WC) buffers and in the Invalid (I) state in the L2 cache and its adjacent sector (B) is in the Invalid (I) state and the following scenario occurs: 1. A read to B misses in the L2 cache and allocates cacheline B and its associated second-sector pre-fetch into an almost full bus queue, 2. A Bus Read Line (BRL) to cacheline B completes with HIT# and fills data in Shared (S) state, 3. The bus queue full condition causes the prefetch to cacheline A to be cancelled, cacheline A will remain M in the WC buffers and I in the L2 while cacheline B will be in the S state. Then, if the further conditions occur: 4. Cacheline A is evicted from the WC Buffers to the bus queue which is still almost full, 5. A hardware prefetch Read for Ownership (RFO) to cacheline B, hits the S state in the L2 and observes cacheline A in the I state, allocates both cachelines, 6. An RFO to cacheline A completes before the WC Buffers write modified data back, filling the L2 with stale data, 7. The writeback from the WC Buffers completes leaving stale data, for cacheline A, in the Exclusive (E) state in the L2 cache. Implication: Stale data may be consumed leading to unpredictable program execution. Intel has not been able to reproduce this erratum with commercial software. Workaround: It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AC37. Simultaneous Assertion of A20M# and INIT# May Result in Incorrect Data Fetch Problem: If A20M# and INIT# are simultaneously asserted by software, followed by a data access to the 0xFFFFFXXX memory region, with A20M# still asserted, incorrect data will be accessed. With A20M# asserted, an access to 0xFFFFFXXX should result in a load from physical address 0xFFEFFXXX. However, in the case of A20M# and INIT# being asserted together, the data load will actually be from the physical address 0xFFFFFXXX. Code accesses are not affected by this erratum Implication: Processor may fetch incorrect data, resulting in BIOS failure. Workaround: Deasserting and reasserting A20M# prior to the data access will workaround this erratum. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Celeron® Processor in the 478-Pin Package Specification Update 33

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Errata
R
Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
33
AC36.
L2 Cache May Contain Stale Data in the Exclusive State
Problem:
If a cacheline (A) is in Modified (M) state in the write-combining (WC) buffers and in the Invalid
(I) state in the L2 cache and its adjacent sector (B) is in the Invalid (I) state and the following
scenario occurs:
1.
A read to B misses in the L2 cache and allocates cacheline B and its associated second-sector
pre-fetch into an almost full bus queue,
2.
A Bus Read Line (BRL) to cacheline B completes with HIT# and fills data in Shared (S)
state,
3.
The bus queue full condition causes the prefetch to cacheline A to be cancelled, cacheline A
will remain M in the WC buffers and I in the L2 while cacheline B will be in the S state.
Then, if the further conditions occur:
4.
Cacheline A is evicted from the WC Buffers to the bus queue which is still almost full,
5.
A hardware prefetch Read for Ownership (RFO) to cacheline B, hits the S state in the L2 and
observes cacheline A in the I state, allocates both cachelines,
6.
An RFO to cacheline A completes before the WC Buffers write modified data back, filling
the L2 with stale data,
7.
The writeback from the WC Buffers completes leaving stale data, for cacheline A, in the
Exclusive (E) state in the L2 cache.
Implication:
Stale data may be consumed leading to unpredictable program execution. Intel has not been able
to reproduce this erratum with commercial software.
Workaround:
It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC37.
Simultaneous Assertion of A20M# and INIT# May Result in Incorrect Data
Fetch
Problem:
If A20M# and INIT# are simultaneously asserted by software, followed by a data access to the
0xFFFFFXXX memory region, with A20M# still asserted, incorrect data will be accessed. With
A20M# asserted, an access to 0xFFFFFXXX should result in a load from physical address
0xFFEFFXXX. However, in the case of A20M# and INIT# being asserted together, the data load
will actually be from the physical address 0xFFFFFXXX. Code accesses are not affected by this
erratum
Implication:
Processor may fetch incorrect data, resulting in BIOS failure.
Workaround:
Deasserting and reasserting A20M# prior to the data access will workaround this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes.