LG 50PC1DR Owners Manual - Page 34

Input Voltages from the Y SUS Board, Voltages Developed on the Z SUS Board - capacitors

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Input Voltages from the Y SUS Board Troubleshooting VS Supplied to IC7 the SUS_IPM through coil FL152 and to the Primary Winding of Transformer T2 of the Z Bias Circuit. Input measured from P151 pin 12 to chassis ground. VA Supplied to the ER_IPM through parallel resistors R91 and R9 and through Diode D84. The VA voltage is also routed to connectors P152 and P153 at pin 7 of each connector. Used to supply 60v to the Center and Bottom Right X Boards. Input measured from pins 8 and 9 of P151 to chassis ground. 5v Used to Bias the circuits on the Z SUS Board and through P152 and P153 pins 3 and 4 supplies 5v to bias the Center and Right X Boards. Input measured from P151 pins 1 and 2 to chassis Voltages Developed on the Z SUS Board Z Bias 90v used to Bias the output circuits that drive the Sustain and Erase pulses for the PDP. Measured across parallel resistors R25 and R111, adjusted at VR3. IPM 18v Needed to generate the Sustain and Erase pulses in the IPMs. Measured at right side of resistor R100 (above capacitor C27). Plasma Display Panel Troubleshooting - 2007 34

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34
Plasma Display Panel Troubleshooting - 2007
Input Voltages from the Y SUS Board
Troubleshooting
VS
Supplied to IC7 the SUS_IPM through coil FL152 and to the Primary Winding of Transformer
T2 of the Z Bias Circuit. Input measured from P151 pin 12 to chassis ground.
VA
Supplied to the ER_IPM through parallel resistors R91 and R9 and through Diode D84. The VA
voltage is also routed to connectors P152 and P153 at pin 7 of each connector. Used to supply
60v to the Center and Bottom Right X Boards. Input measured from pins 8 and 9 of
P151 to
chassis ground.
5v
Used to Bias the circuits on the Z SUS Board and through P152 and P153 pins 3 and 4
supplies 5v to bias the Center and Right X Boards. Input measured from P151 pins 1 and 2 to
chassis
Voltages Developed on the Z SUS Board
Z
Bias
90v used to Bias the output circuits that drive the Sustain and Erase pulses for the PDP.
Measured across parallel resistors R25 and R111, adjusted at VR3.
IPM 18v
Needed to generate
the Sustain and Erase pulses in the IPMs. Measured at right side of
resistor R100 (above capacitor C27).