MSI H55M User Guide - Page 59

CH1/ CH2 CAS Latency CL

Page 59 highlights

MS-7636 PROM on the DRAM module. Setting to [Auto] enables DRAM timings and the following "Advance DRAM Configuration" sub-menu to be determined by BIOS based on the configurations on the SPD. Selecting [Manual] allows users to configure the DRAM timings and the following related "Advance DRAM Configuration" sub-menu manually. ▶ Advance DRAM Configuration Press to enter the sub-menu. ▶ CH1/ CH2 1T/2T Memory Timing This item controls the SDRAM command rate. Select [1N] makes SDRAM signal controller to run at 1N (N=clock cycles) rate. Selecting [2N] makes SDRAM signal controller run at 2N rate. ▶ CH1/ CH2 CAS Latency (CL) This controls the CAS latency, which determines the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. ▶ CH1/ CH2 tRCD When DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. ▶ CH1/ CH2 tRP This setting controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. ▶ CH1/ CH2 tRAS This setting determines the time RAS takes to read from and write to memory cell. ▶ CH1/ CH2 tRFC This setting determines the time RFC takes to read from and write to a memory cell. ▶ CH1/ CH2 tWR Minimum time interval between end of write data burst and the start of a precharge command. Allows sense amplifiers to restore data to cells. ▶ CH1/ CH2 tWTR Minimum time interval between the end of write data burst and the start of a column-read command. It allows I/O gating to overdrive sense amplifiers before read command starts. ▶ CH1/ CH2 tRRD Specifies the active-to-active delay of different banks. ▶ CH1/ CH2 tRTP Time interval between a read and a precharge command. ▶ CH1/ CH2 tFAW This item is used to set the tFAW timing. ▶ Current CH1/ CH2 tdrRdTRd/ tddRdTRd/ tsrRdTWr/ tdrRdTWr/ tddRdTWr/ 3-21

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3-21
MS-7636
PROM on the DRAM module. Sett±ng to [Auto] enables DRAM t±m±ngs and the follow±ng
“Advance DRAM Configurat±on” sub-menu to be determ±ned by BIOS based on the con-
figurat±ons on the SPD. Select±ng [Manual] allows users to configure the DRAM t±m±ngs
and the follow±ng related “Advance DRAM Configurat±on” sub-menu manually.
Advance DRAM Configurat±on
Press <Enter> to enter the sub-menu.
CH1/ CH2 1T/2T Memory T±m±ng
Th±s ±tem controls the SDRAM command rate. Select [1N] makes SDRAM s±gnal
controller to run at 1N (N=clock cycles) rate. Select±ng [2N] makes SDRAM s±gnal
controller run at 2N rate.
CH1/ CH2 CAS Latency (CL)
Th±s controls the CAS latency, wh±ch determ±nes the t±m±ng delay (±n clock cycles)
before SDRAM starts a read command after rece±v±ng ±t.
CH1/ CH2 tRCD
When DRAM ±s refreshed, both rows and columns are addressed separately. Th±s
setup ±tem allows you to determ±ne the t±m±ng of the trans±t±on from RAS (row ad-
dress strobe) to CAS (column address strobe). The less the clock cycles, the faster
the DRAM performance.
CH1/ CH2 tRP
Th±s sett±ng controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If ±nsuffic±ent t±me ±s allowed for the RAS to accumulate ±ts
charge before DRAM refresh, refresh may be ±ncomplete and DRAM may fa±l to
reta±n data. Th±s ±tem appl±es only when synchronous DRAM ±s ±nstalled ±n the sys-
tem.
CH1/ CH2 tRAS
Th±s sett±ng determ±nes the t±me RAS takes to read from and wr±te to memory cell.
CH1/ CH2 tRFC
Th±s sett±ng determ±nes the t±me RFC takes to read from and wr±te to a memory
cell.
CH1/ CH2 tWR
M±n±mum t±me ±nterval between end of wr±te data burst and the start of a precharge
command. Allows sense ampl±fiers to restore data to cells.
CH1/ CH2 tWTR
M±n±mum t±me ±nterval between the end of wr±te data burst and the start of a col-
umn-read command. It allows I/O gat±ng to overdr±ve sense ampl±fiers before read
command starts.
CH1/ CH2 tRRD
Spec±fies the act±ve-to-act±ve delay of d±fferent banks.
CH1/ CH2 tRTP
T±me ±nterval between a read and a precharge command.
CH1/ CH2 tFAW
Th±s ±tem ±s used to set the tFAW t±m±ng.
Current CH1/ CH2 tdrRdTRd/ tddRdTRd/ tsrRdTWr/ tdrRdTWr/ tddRdTWr/