MSI K8T NEO2-FIR User Guide - Page 59

MS-6702E ATX Mainboard CAS Latency This controls the CAS latency, which determines the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. Settings: [SPD], [2], [3], and [2.5]. [2] increases the system performance the most while [3] provides the most stable performance. Burst Length This setting allows you to set the size of Burst-Length for DRAM. Bursting feature is a technique that DRAM itself predicts the address of the next memory location to be accessed after the first address is accessed. To use the feature, you need to define the burst length, which is the actual length of burst plus the starting address and allows internal address counter to properly generate the next memory location. The bigger the size, the faster the DRAM performance. Settings: [8 beat] and [4 beat]. Bank Interleaving This field selects 2-bank or 4-bank interleave for the installed SDRAM. Disable the function if 16MB SDRAM is installed. Settings: [Auto] and [Disabled]. Active to CMD (Trcd) When DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. Setting options: [SPD], [2 CLK], [3 CLK], [4 CLK], [5 CLK], and [6 CLK]. Active to Precharge (Tras) This setting determines the time RAS takes to read from and write to a memory cell. Setting options: [SPD], [5 CLK], [6 CLK], [7 CLK], [8 CLK], [9 CLK], [10 CLK], [11 CLK], [12 CLK], [13 CLK], [14 CLK], [15 CLK]. Precharge to Active (Trp) This item controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refreshing may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. Available settings: [SPD], [2 CLK], [3 CLK], [4 CLK], [5 CLK], [6 CLK]. DRAM 1T Timing This setting is to enable/disable the SDRAM signal controller run at 1T (T=clock cycles) rate. Selecting [1T] makes SDRAM signal controller run at 2T rate. 1T is faster than 2T. Setting options: [Enabled], [Disabled]. High Performance Mode This field allows you to select the DDR timing setting. Setting to [Optimized] enables Adjust DDR Memory Frequency automatically to be determined by SPD. Selecting [Manual] allows users to configure these fields manually. Setting options: [Optimized], [Manual]. 3-20