Sony PCV-R526DS Reference Manual - Page 89

Chipset Features Setup Screen

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CMOS Setup Options 81 CHIPSET FEATURES SETUP Screen SDRAM Configuration: SDRAM CAS Latency: SDRAM RAS to CAS Delay:* SDRAM RAS Precharge Time:* DRAM Idle Timer:* SDRAM MA Wait State: Graphics Aperture Size: Video Memory Cache Mode: PCI 2.1 Support: DRAM are 64 (Not 72) bits wide Data Integrity Mode: Onboard FDC Controller: [By SPD] Disabled 7ns (143MHz) 8ns (125MHz) [3T] 2T [2T] 3T [2T] 3T [10T] 12T 16T 32T Infinite 0T 2T 4T 8T [Normal] Slow Fast [64MB] 128MB 256MB 4MB 8MB 16MB 32MB [UC] USWC [Enabled] Disabled Non-ECC [Enabled] Disabled * These settings depend on the setting in SDRAM Configuration, and become enabled only when SDRAM Configuration is Disabled.

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CMOS Setup Options
81
CHIPSET FEATURES SETUP Screen
SDRAM Configuration:
[By SPD]
Disabled
7ns (143MHz)
8ns (125MHz)
SDRAM CAS Latency:
[3T]
2T
SDRAM RAS to CAS Delay:
*
[2T]
3T
SDRAM RAS Precharge Time:
*
[2T]
3T
DRAM Idle Timer:
*
[10T]
12T
16T
32T
Infinite
0T
2T
4T
8T
SDRAM MA Wait State:
[Normal]
Slow
Fast
Graphics Aperture Size:
[64MB]
128MB
256MB
4MB
8MB
16MB
32MB
Video Memory Cache Mode:
[UC]
USWC
PCI 2.1 Support:
[Enabled]
Disabled
DRAM are 64 (Not 72) bits wide
Data Integrity Mode:
Non-ECC
Onboard FDC Controller:
[Enabled]
Disabled
*
These settings depend on the setting in SDRAM Configuration, and become enabled only when
SDRAM Configuration is Disabled.