Via EPIA-CN13000G User Manual - Page 48
V-Link mode selection, V-Link 8X Support, DRDY_Timing
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Chapter 3 CPU & PCI BUS CONTROL VLink mode selection VLink 8X Support DRDY_Timing Phoenix - AwardBIOS CMOS Setup Utility CPU & PCI Bus Control [By Auto] [Enabled] [Default] Item Help Menu Level : Move Enter: Select F5: Previous Values +/-/PU/PD: Value F10: Save F6: Fail-Safe Defaults ESC: Exit F1: General F7: Optimized Defaults Help V-Link mode selection This menu item controls the data transfer speed between the north and south bridge. Settings: [By Auto, Mode 0~4] V-Link 8X Support Settings: [Enabled, Disabled] DRDY_Timing Settings: [Slowest, Default, Optimize] 40
Chapter 3
40
CPU
&
PCI
B
US
C
ONTROL
: Move
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Enter: Select
+/-/PU/PD: Value
F10: Save
ESC: Exit
F1: General
Help
Menu Level
Item Help
[By Auto]
VLink mode selection
CPU & PCI Bus Control
Phoenix - AwardBIOS CMOS Setup Utility
VLink 8X Support
[Enabled]
DRDY_Timing
[Default]
V-Link mode selection
This menu item controls the data transfer speed between the north and south
bridge.
Settings: [By Auto, Mode 0~4]
V-Link 8X Support
Settings: [Enabled, Disabled]
DRDY_Timing
Settings: [Slowest, Default, Optimize]