Via EPIA-EN12000EG User Manual - Page 73

DRAM Clock, DRAM Timing, SDRAM CAS Latency [DDR/DDR2]

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FREQUENCY / VOLTAGE CONTROL BIOS Setup Phoenix - AwardBIOS CMOS Setup Utility Frequency / Voltage Control DRAM Clock DRAM Timing SDRAM CAS Latency [DDR/DDR2] Bank Interleave Precharge to Active(Trp) Active to Precharge(Tras) Active to CMD(Trcd) REF to ACT/REF(Trfc) ACT(0) to ACT(1) (TRRD) Read to Precharge(Trtp) Write to Read CMD(Twtr) Write Recovery Time(Twr) DRAM Command Rate RDSAIT mode RDSAIT selection Auto Detect PCI Clk [By SPD] [Auto By SPD] 2.5/ 4 Disabled 4T 07T 4T 25T 3T [2T] [1T/2T] [4T] [2T Command] [Auto] 03 [Enabled] Item Help Menu Level Spread Spectrum [0.25%] : Move Enter: Select F5: Previous Values +/-/PU/PD: Value F10: Save F6: Fail-Safe Defaults ESC: Exit F1: General F7: Optimized Defaults Help DRAM Clock The chipset supports synchronous and asynchronous mode between host clock and DRAM clock frequency. Settings: [100 MHz, 133 MHz, 166 MHz, 200MHz, 266MHz, 333MHz, By SPD] DRAM Timing The value in this field depends on the memory modules installed in your system. Changing the value from the factory setting is not recommended unless you install new memory that has a different performance rating than the original modules. Settings: [Manual, Auto By SPD, Turbo, Ultra] SDRAM CAS Latency [DDR/DDR2] This item is for setting the speed it takes for the memory module to complete a command. Generally, a lower setting will improve the performance of your system. However, if your system becomes less stable, you should change it to a higher setting. This field is only available when "DRAM Timing" is set to "Manual". Settings: [1.5/2, 2/3, 2.5/4, 3/5] 65

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BIOS Setup
65
F
REQUENCY
/
V
OLTAGE
C
ONTROL
: Move
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Enter: Select
+/-/PU/PD: Value
F10: Save
ESC: Exit
F1: General
Help
Menu Level
Item Help
DRAM Clock
[By SPD]
DRAM Timing
[Auto By SPD]
Bank Interleave
Disabled
Precharge to Active(Trp)
4T
Active to Precharge(Tras)
07T
Active to CMD(Trcd)
4T
REF to ACT/REF(Trfc)
25T
ACT(0) to ACT(1) (TRRD)
3T
SDRAM CAS Latency [DDR/DDR2]
2.5/ 4
Frequency / Voltage Control
Phoenix - AwardBIOS CMOS Setup Utility
Spread Spectrum
[0.25%]
Read to Precharge(Trtp)
[2T]
Write to Read CMD(Twtr)
[1T/2T]
Write Recovery Time(Twr)
[4T]
DRAM Command Rate
[2T Command]
RDSAIT mode
[Auto]
RDSAIT selection
03
Auto Detect PCI Clk
[Enabled]
DRAM Clock
The chipset supports synchronous and asynchronous mode between host
clock and DRAM clock frequency.
Settings: [100 MHz, 133 MHz, 166 MHz, 200MHz, 266MHz, 333MHz, By SPD]
DRAM Timing
The value in this field depends on the memory modules installed in your
system.
Changing the value from the factory setting is not recommended
unless you install new memory that has a different performance rating than
the original modules.
Settings: [Manual, Auto By SPD, Turbo, Ultra]
SDRAM CAS Latency [DDR/DDR2]
This item is for setting the speed it takes for the memory module to complete
a command.
Generally, a lower setting will improve the performance of your
system.
However, if your system becomes less stable, you should change it
to a higher setting.
This field is only available when “DRAM Timing” is set to
“Manual”.
Settings: [1.5/2, 2/3, 2.5/4, 3/5]