Via NR10000EG User Manual - Page 64

DRAM Clock, DRAM Timing, SDRAM CAS Latency [DDR/DDR2], Bank Interleave, Precharge to Active Trp

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Page 64 highlights

Chapter 3 DRAM CLOCK/DRIVE CONTROL Phoenix - AwardBIOS CMOS Setup Utility PnP / PCI Configurations DRAM Clock DRAM Timing SDRAM CAS Latency [DDR/DDR2] Bank Interleave Precharge to Active(Trp) Active to Precharge(Tras) Active to CMD(Trcd) REF to ACT/REF (Trfc) ACT(0) to ACT(1) (TRRD) Read to Precharge (Trtp) Write to read CMD (Twtr) Write Recovery Time (Twr) RDSAIT mode x RDSAIT selection [By SPD] [Manual] [2.5 / 4] [Disabled] [4T] [07T] [4T] [25T] [3T] [2T] [1T/2T] [4T] [Auto] 03 Item Help Menu Level : Move Enter: Select F5: Previous Values +/-/PU/PD: Value F10: Save F6: Fail-Safe Defaults ESC: Exit F1: General Help F7: Optimized Defaults DRAM Clock The chipset supports synchronous and asynchronous mode between host clock and DRAM clock frequency. Settings: [By SPD, 100 MHz, 133 MHz, 166 MHz, 200MHz, 266MHz, 333MHz] DRAM Timing The value in this field depends on the memory modules installed in your system. Changing the value from the factory setting is not recommended unless you install new memory that has a different performance rating than the original modules. Settings: [Manual, Auto By SPD] SDRAM CAS Latency [DDR/DDR2] Settings: [1.5/2, 2/3, 2.5/4, 3/5] Bank Interleave Settings: [Disabled, 2 Bank, 4 Bank, 8 Bank] Precharge to Active (Trp) Settings: [2T, 3T, 4T, 5T] 56

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Chapter 3
56
DRAM
C
LOCK
/D
RIVE
C
ONTROL
: Move
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Enter: Select
+/-/PU/PD: Value
F10: Save
ESC: Exit
F1: General Help
Menu Level
Item Help
DRAM Clock
[By SPD]
DRAM Timing
[Manual]
Bank Interleave
[Disabled]
Precharge to Active(Trp)
[4T]
Active to CMD(Trcd)
[4T]
PnP / PCI Configurations
Phoenix - AwardBIOS CMOS Setup Utility
REF to ACT/REF (Trfc)
[25T]
ACT(0) to ACT(1) (TRRD)
[3T]
Write to read CMD (Twtr)
Write Recovery Time (Twr)
[4T]
RDSAIT mode
[Auto]
SDRAM CAS Latency [DDR/DDR2]
[2.5 / 4]
Active to Precharge(Tras)
[07T]
Read to Precharge (Trtp)
[2T]
x RDSAIT selection
03
[1T/2T]
DRAM Clock
The chipset supports synchronous and asynchronous mode between host
clock and DRAM clock frequency.
Settings: [By SPD, 100 MHz, 133 MHz, 166 MHz, 200MHz, 266MHz, 333MHz]
DRAM Timing
The value in this field depends on the memory modules installed in your
system.
Changing the value from the factory setting is not recommended
unless you install new memory that has a different performance rating than
the original modules.
Settings: [Manual, Auto By SPD]
SDRAM CAS Latency [DDR/DDR2]
Settings: [1.5/2, 2/3, 2.5/4, 3/5]
Bank Interleave
Settings: [Disabled, 2 Bank, 4 Bank, 8 Bank]
Precharge to Active (Trp)
Settings: [2T, 3T, 4T, 5T]