ViewSonic VA902B Service Manual - Page 9

dimming frequency is determined by R527 and C506. C502 is used for soft start and compensation, C502, C528 are used to filter noise. The output drives, including NDR4, NDRV2, PDRV3, PDRV1 (pins1, 3, 15, 16 respectively), generate a square pulses to drive MOSFET U501, U502. And U501, U502 works as full-bridge topology, it is high efficient, zero voltage switch. During start up, VSEN (pin9) detects the voltage at the transformer secondary. When VSEN reaches 3.0V, the output voltage is regulated. If no current is detected for around 1.5 seconds, IC501 will shut down. The current flowing through CCFL is detected and regulated through sense resistor R509, R511. The feedback voltage through R506, R507, and C508 connected to Pin11 (ISEN), and then compared with a reference voltage (1.5V) via a current amplifier, resulting in PWM drive outputs to full-bridge switches. 2.2.2 Protection circuit Over Voltage Protection: R501and R502 are connected in high voltage output connector, the divided AC voltage is inverted DC voltage through D508, R505 and C507are used to rectify wave & dump noise. Then the voltage signal reaches Pin9 VSEN of IC501, when the voltage changes, build-in PWM of IC501 will adjust output voltage. Open Lamp Protection: In normal operation, the resistors R510, R511, R512, R509 are sensed a high level AC voltage, the AC signal IS1 invert DC voltage through D509, R515, C533, and the high level DC voltage reaches the gate pin of Q502, similarly, the gate pin of Q503, Q504, Q505 has high level DC voltage. So the gate pin of Q501 has a low level voltage, and the IC501 is normal operation. Once one of signal IS1, IS2, IS3, and IS4 is low, the voltages of Q501 gate pin is high level, and make the voltage of ISEN low level, the IC501 will shut down. 2.3 I/F Board Circuit 2.3.1 Power Input +5V is from the power board and supply for U101(FS8860-18PJ)﹑U102(FS8860-33PJ)﹑ U105(MCU:W78E65P) and panel. +3.3V output is generated from +5V through C169 and C102 filtering, and U102 outputs. +3.3V is used for U104 (Scaler: TSU16AK). +1.8V output is generated from +5V through C169, C105 and C102 filtering, and U101 outputs. +1.8V is also used for U104. 2.3.2 MCU (W78E65P) VDD is +5V and its frequency of XTAL1 is 22.1184MHz. U105 #2 is defined as panel-enable. When the I/O port is low, Q101 and Q102 are conducted. And then after C109 and C110 filtering, obtain the voltage of VLCD, which will be connected to CN103. U105 #3 is defined as CCFL-enable. When the I/O port is low, Q103 is pulled up and the backlights are on; When the I/O port is high, Q103 is conducted and the backlights are off. U105 #4 is defined as DET-VGA, connected with CN102 #5. U105 #14, #36, #37, #38, #39, #40, #41, #42, #43 are the communications with U104 (Scaler), which are connected to #72, #31, #78, #77, #30, #70, #71, #69, #32 of Scaler. U105 #43 outputs reset signal to U104 (Scaler). U106 is EEPROM used for saving EDID data, which is connected by SCL and SDA pins with #16 and #17 of MCU. Connect #12 to #26 of U105 for ISP. 2.3.3 Scaler (TSU16AK) The frequency of XTAL2 is 14.318MHz. U104 #1, #102-#103, #106-#113, #118-#125, #128 output LVDS digital data of 8 bit to panel control circuit through CN103. U104 #73 generates a PWM waveform by regulating the duty to control the brightness of the backlights. U104 #30-#32, #69-#72, #77-#78 are the communications with U105 (MCU) that are connected to #36-#43 of MCU. These communications include HWRESET, CSZ/ALE, SCL/RDZ, SDA/WRZ, and AD0-AD3. 2.3.4 VGA Input Signal R, G, B, SOG input through CN102 #1, #2, #3, and C115, C116, C117 and C118 filtering the high frequency noise. Signal HSYNC and VSYNC input through CN102 #13 and #14, and C119, R119, C120, R120 filtering. Then the analog signal enters U104, and then U104 deals with it internally. In addition, TVS101, TVS102, TVS103 (the three are BAV99), TVS104, TVS105, TVS106, TVS107 (they are constant voltage diode of 5V6) are ESD protector. Signal DDC-SCL inputs via CN102 #15, and then passes through TVS107 for ESD protection, goes into EDID EEPROM IC U103. Signal DDC-SDA inputs via CN102 #12, and then passes through TVS106 for ESD protection, goes into EDID EEPROM IC U103. CN102 #5 is defined as cable detect pin, this detector realizes via R107 and U105 #4. The PC-5V of U103 is supplied by PC via CN103 #9 with D103 for ESD protection, or supplied by Monitor self via D104.U103 is an EEPROM IC, which is a kind of memory and used for saving EDID data. 2.3.5 Button Control Button "Key-Power" is defined as power on/off, which is connected to U105 #24 through CN106 #4. ViewSonic Corporation Confidential - Do Not Copy VA902/b 6