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Product, Errata

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Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 Product Errata This section documents product errata for the processors. A unique tracking number for each erratum has been assigned within this document for user convenience in tracking the errata within specific revision levels. This table cross-references the revisions of the part to each erratum. "No fix planned" indicates that no fix is planned for current or future revisions of the processor. Note: There may be missing errata numbers. Errata that do not affect this product family do not appear. In addition, errata that have been resolved from early revisions of the processor have been deleted, and errata that have been reconsidered may have been deleted or renumbered. Table 7. Cross-Reference of Processor Revision to Errata CPUID Fn0000_0001_EAX, D18F4x164[1:0] No. Errata Description 00600F12h 01b (OR-B2) 00600F20h 11b (OR-C0) 361 Breakpoint Due to an Instruction That Has an Interrupt Shadow May Be Lost 503 APIC Task-Priority Register May Be Incorrect 504 Corrected L3 Errors May Lead to System Hang 505 Scrub Rate Control Register Address Depends on DctCfgSel 520 Some Lightweight Profiling Counters Stop Counting When Instruction-Based Sampling is Enabled 535 Lightweight Profiling May Not Indicate Fused Branch 536 Performance Counter for Instruction Cache Misses Does Not Increment for Sequential Prefetches 537 Performance Counter for Ineffective Software Prefetches Does Not Count for L2 Hits 538 Performance Counter Does Not Count for Some Retired Micro-Ops 540 GART Table Walk Probes May Cause System Hang 550 Latency Performance Counters Are Not Accurate 585 Incorrect Memory Controller Operation Due to a WrDatGrossDly Setting of 3.5 MEMCLKs 586 A Far Control Transfer Changing Processor Operating Mode May Generate a False Machine Check 592 VPEXTRQ and VPINSRQ May Not Signal Invalid-Opcode Exception 593 Last-Branch Record Enabled May Cause Machine Check and Incorrect LastBranchToIp 600 HyperTransport™ Link Retry Due to Partial CRC Error May Cause System Hang 602 HyperTransport™ Link Frequency Changes May Cause a System Hang No fix planned No fix planned No fix planned No fix planned X X X X X No fix planned No fix planned No fix planned X X X X No fix planned 14 Product Errata

Section	Page
List of Figures	3
List of Tables	4
Revision History	5
Overview	6
Revision Guide Policy	6
Conventions	7
Numbering	7
Register References and Mnemonics	7
Arithmetic and Logical Operators	8
Processor Identification	9
Revision Determination	9
D18F4x164 Fixed Errata Register	10
Mixed Processor Revision Support	11
Programming and Displaying the Processor Name String	11
Constructing the Processor Name String	11
Operating System Visible Workarounds	13
MSRC001_0140 OS Visible Work-around MSR0 (OSVW_ID_Length)	13
MSRC001_0141 OS Visible Work-around MSR1 (OSVW_Status)	13
Product Errata	14
Cross-Reference of Errata to Package Type	18
Cross-Reference of Errata to Processor Segments	21
361 Breakpoint Due to an Instruction That Has an Interrupt Shadow May Be Lost	24
503 APIC Task-Priority Register May Be Incorrect	25
504 Corrected L3 Errors May Lead to System Hang	26
505 Scrub Rate Control Register Address Depends on DctCfgSel	27
520 Some Lightweight Profiling Counters Stop Counting When Instruction-Based Sampling is Enabled	28
535 Lightweight Profiling May Not Indicate Fused Branch	29
536 Performance Counter for Instruction Cache Misses Does Not Increment for Sequential Prefetches	30
537 Performance Counter for Ineffective Software Prefetches Does Not Count for L2 Hits	31
538 Performance Counter Does Not Count for Some Retired Micro-Ops	32
540 GART Table Walk Probes May Cause System Hang	33
550 Latency Performance Counters Are Not Accurate	34
585 Incorrect Memory Controller Operation Due to a WrDatGrossDly Setting of 3.5 MEMCLKs	35
586 A Far Control Transfer Changing Processor Operating Mode May Generate a False Machine Check	36
592 VPEXTRQ and VPINSRQ May Not Signal Invalid-Opcode Exception	37
593 Last-Branch Record Enabled May Cause Machine Check and Incorrect LastBranchToIp	38
600 HyperTransport™ Link Retry Due to Partial CRC Error May Cause System Hang	39
602 HyperTransport™ Link Frequency Changes May Cause a System Hang	40
608 P-state Limit Changes May Not Generate Interrupts	41
619 Non-Posted Reads May Block Write Dependent on Probe Responses	42
623 Small Code Segment Limits May Cause Incorrect Limit Faults	43
624 SB-RMI Processor State Accesses May Persistently Timeout if Interrupted by a Warm Reset	44
625 SB-RMI Writes May Not Be Observed by Processor	45
636 Instruction Addresses Near Canonical Address Limit May Cause #GP Exception	46
637 Processor Does Not Report the Correct DRAM Address for MCA Errors Within the CC6 Save Area	47
657 MC1_STATUS Enable Bit Not Set When Logging Corrected Errors	49
658 CPUID Incorrectly Reports Large Page Support in L2 Instruction TLB	50
659 VMCB Interrupt Shadow Status May Be Incorrect	51
660 APERF May Increase Unpredictably	52
661 P-State Limit and Stop Clock Assertion May Cause System Hang	53
663 Local Interrupts LINT0/LINT1 May Occur While APIC is Software Disabled	54
667 Processor May Generate Incorrect P-state Limit Interrupts	55
668 Load Operation May Receive Incorrect Data After Floating-point Exception	56
671 Debug Breakpoint on Misaligned Store May Cause System Hang	57
672 SVM Guest Performance Counters May Be Inaccurate Due to SMI	58
673 Misaligned Page Crossing String Operations May Cause System Hang	59
674 Processor May Cache Prefetched Data from Remapped Memory Region	60
675 Instructions Performing Read-Modify-Write May Alter Architectural State Before #PF	61
685 Some Processor Cores May Have Inaccurate Instruction Cache Fetch Performance Counter	62
689 AM3r2 Six Core Processor May Limit P-State When Core C6 State Is Disabled	63
690 Northbridge FIFO Read/Write Pointer Overlap May Cause Hang or Protocol Error Machine Check	64
691 Processors Using 1 MB L3 Subcaches May Execute a Write-Back Invalidate Operation Incorrectly	65
693 Performance Counter May Incorrectly Count MXCSR Loads	66
694 IBS Sampling of Instruction Fetches May Be Uneven	67
695 Processor May Interpret FCW Incorrectly after FNSAVE/FSAVE Limit Fault	68
699 Processor May Generate Illegal Access in VMLOAD or VMSAVE Instruction	69
704 Processor May Report Incorrect Instruction Pointer	70
707 Performance Counter for Locked Operations May Count Cycles from Non-Locked Operations	71
708 Initial Value of Time Stamp Counter May Include an Offset Error	72
709 Processor May Be Limited to Minimum P-state After a P-state Limit Change	73
714 Processor May Check DRAM Address Maps While Using L2 Cache as General Storage during Boot	74
717 Instruction-Based Sampling May Be Inaccurate	75
718 Instruction-Based Sampling May Be Inaccurate	76
719 Instruction-Based Sampling Fetch Counter Always Starts at Maximum Value	77
720 Processor May Not Respect Interrupt Shadow	78
724 Unintercepted Halt Instruction May Cause Protocol Machine Check or Unpredictable System Behavior	79
725 Incorrect APIC Remote Read Behavior	80
726 Processor May Report Incorrect MCA Address for Loads that Cross Address Boundaries	81
727 Processor Core May Hang During CC6 Resume	82
734 Processor May Incorrectly Store VMCB Data	83
737 Processor Does Not Check 128-bit Canonical Address Boundary Case on Logical Address	84
739 Processor May Read Branch Status Register With Inconsistent Parity Bit	85
740 Lightweight Profiling May Cause System Hang with Concurrent Stop Clock	86
742 DRAM Scrub Request During Register Write May Cause Unpredictable Behavior	87
744 Processor CC6 May Not Restore Trap Registers	88
745 Processor May Incorrectly Report Cache Sharing Property in CPUID Topology	89
759 One Core May Observe a Time Stamp Counter Skew	90

Match case Limit results 1 per page

Product

Errata

This

section

documents

product

errata

for

the

processors

unique

tracking

number

for

each

erratum

has

been

assigned

within

this

document

for

user

convenience

tracking

the

errata

within

specific

revision

levels

This

table

cross-references

the

revisions

the

part

each

erratum

"No

fix

planned"

indicates

that

fix

planned

for

current

future

revisions

the

processor

Note

There

may

missing

errata

numbers

Errata

that

not

affect

this

product

family

not

appear

addition

errata

that

have

been

resolved

from

early

revisions

the

processor

have

been

deleted

and

errata

that

have

been

reconsidered

may

have

been

deleted

renumbered

Table

Cross-Reference

Processor

Revision

Errata

Description

CPUID

0000_0001_

EAX

164[1:0]

00600

(

OR-B

00600

(

OR-C

361

Breakpoint

Due

Instruction

That

Has

Interrupt

Shadow

May

Lost

fix

planned

503

APIC

Task-Priority

May

Incorrect

fix

planned

504

Corrected

Errors

May

Lead

System

Hang

fix

planned

505

Scrub

Rate

Control

Address

Depends

DctCfgSel

fix

planned

520

Some

Lightweight

Profiling

Counters

Stop

Counting

When

Instruction-Based

Sampling

Enabled

535

Lightweight

Profiling

May

Not

Indicate

Fused

Branch

536

Performance

Counter

for

Instruction

Cache

Misses

Does

Not

Increment

for

Sequential

Prefetches

537

Performance

Counter

for

Ineffective

Software

Prefetches

Does

Not

Count

for

Hits

538

Performance

Counter

Does

Not

Count

for

Some

Retired

Micro-Ops

540

GART

Table

Walk

Probes

May

Cause

System

Hang

fix

planned

550

Latency

Performance

Counters

Are

Not

Accurate

fix

planned

585

Incorrect

Memory

Controller

Operation

Due

WrDatGrossDly

Setting

3.5

MEMCLKs

fix

planned

586

Far

Control

Transfer

Changing

Processor

Operating

Mode

May

Generate

False

Machine

Check

592

VPEXTRQ

and

VPINSRQ

May

Not

Signal

Invalid-Opcode

Exception

593

Last-Branch

Record

Enabled

May

Cause

Machine

Check

and

Incorrect

LastBranchToIp

600

HyperTransport

™

Link

Retry

Due

Partial

CRC

Error

May

Cause

System

Hang

602

HyperTransport

™

Link

Frequency

Changes

May

Cause

System

Hang

fix

planned

Revision

Guide

for

AMD

Family

Models

Processors

48063

Rev

. 3.18

October

2012

Product

Errata