AMD 3200 Revision History - Page 15
Table, Cross-Reference, Processor, Revision, Errata, continued
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48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors Table 7. Cross-Reference of Processor Revision to Errata (continued) CPUID Fn0000_0001_EAX, D18F4x164[1:0] No. Errata Description 00600F12h 01b (OR-B2) 00600F20h 11b (OR-C0) 608 P-state Limit Changes May Not Generate Interrupts 619 Non-Posted Reads May Block Write Dependent on Probe Responses 623 Small Code Segment Limits May Cause Incorrect Limit Faults 624 SB-RMI Processor State Accesses May Persistently Timeout if Interrupted by a Warm Reset 625 SB-RMI Writes May Not Be Observed by Processor 636 Instruction Addresses Near Canonical Address Limit May Cause #GP Exception 637 Processor Does Not Report the Correct DRAM Address for MCA Errors Within the CC6 Save Area 657 MC1_STATUS Enable Bit Not Set When Logging Corrected Errors 658 CPUID Incorrectly Reports Large Page Support in L2 Instruction TLB 659 VMCB Interrupt Shadow Status May Be Incorrect 660 APERF May Increase Unpredictably 661 P-State Limit and Stop Clock Assertion May Cause System Hang 663 Local Interrupts LINT0/LINT1 May Occur While APIC is Software Disabled 667 Processor May Generate Incorrect P-state Limit Interrupts 668 Load Operation May Receive Incorrect Data After Floating-point Exception 671 Debug Breakpoint on Misaligned Store May Cause System Hang 672 SVM Guest Performance Counters May Be Inaccurate Due to SMI 673 Misaligned Page Crossing String Operations May Cause System Hang 674 Processor May Cache Prefetched Data from Remapped Memory Region 675 Instructions Performing Read-Modify-Write May Alter Architectural State Before #PF 685 Some Processor Cores May Have Inaccurate Instruction Cache Fetch Performance Counter 689 AM3r2 Six Core Processor May Limit P-State When Core C6 State Is Disabled 690 Northbridge FIFO Read/Write Pointer Overlap May Cause Hang or Protocol Error Machine Check No fix planned X X X No fix planned X No fix planned No fix planned X X X No fix planned No fix planned No fix planned X X X X X X X X No fix planned Product Errata 15