ASRock A620M Pro RS Software/BIOS Setup Guide - Page 36

TrdrdScL, TwrwrScL, °e minimum number of cycles from the last clock of virtual CAS of a first write

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TrdrdScL The minimum number of cycles from the last clock of virtual CAS of the first readburst operation to the clock in which CAS is asserted for a following read-burst operation in the same chipselect in the same bank group. TrdrdSc The minimum number of cycles from the last clock of virtual CAS of the first readburst operation to the clock in which CAS is asserted for a following read-burst operation in the same chipselect. TrdrdSd The minimum number of cycles from the last clock of virtual CAS of the first readburst operation to the clock in which CAS is asserted for a following read-burst operation in the same DIMM. TrdrdDd The minimum number of cycles from the last clock of virtual CAS of the first readburst operation to the clock in which CAS is asserted for a following read-burst operation in a different DIMM. TwrwrScL The minimum number of cycles from the last clock of virtual CAS of a first writeburst operation to the clock in which CAS is asserted for a following write-burst operation in the same bank group. TwrwrSc The minimum number of cycles from the last clock of virtual CAS of the first writeburst operation to the clock in which CAS is asserted for a following write-burst operation in the same chipselect. TwrwrSd The minimum number of cycles from the last clock of virtual CAS of the first writeburst operation to the clock in which CAS is asserted for a following write-burst operation in the same DIMM. TwrwrDd The minimum number of cycles from the last clock of virtual CAS of the first writeburst operation to the clock in which CAS is asserted for a following write-burst operation in a different DIMM. 32

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32
TrdrdScL
°e minimum number of cycles from the last clock of virtual CAS of the first read-
burst operation to the clock in which CAS is asserted for a following read-burst
operation in the same chipselect in the same bank group.
TrdrdSc
°e minimum number of cycles from the last clock of virtual CAS of the first read-
burst operation to the clock in which CAS is asserted for a following read-burst
operation in the same chipselect.
TrdrdSd
°e minimum number of cycles from the last clock of virtual CAS of the first read-
burst operation to the clock in which CAS is asserted for a following read-burst
operation in the same DIMM.
TrdrdDd
°e minimum number of cycles from the last clock of virtual CAS of the first read-
burst operation to the clock in which CAS is asserted for a following read-burst
operation in a different DIMM.
TwrwrScL
°e minimum number of cycles from the last clock of virtual CAS of a first write-
burst operation to the clock in which CAS is asserted for a following write-burst
operation in the same bank group.
TwrwrSc
°e minimum number of cycles from the last clock of virtual CAS of the first write-
burst operation to the clock in which CAS is asserted for a following write-burst
operation in the same chipselect.
TwrwrSd
°e minimum number of cycles from the last clock of virtual CAS of the first write-
burst operation to the clock in which CAS is asserted for a following write-burst
operation in the same DIMM.
TwrwrDd
°e minimum number of cycles from the last clock of virtual CAS of the first write-
burst operation to the clock in which CAS is asserted for a following write-burst
operation in a different DIMM.