ASRock B85M-ITX User Manual - Page 65

FIVR Switch Frequency Offset

Page 65 highlights

B85M-ITX Configure IO latency for channel A. IO-L (CHB) Configure IO latency for channel B. ODT WR (CHA) Configure the memory on die termination resistors' WR for channel A. ODT WR (CHB) Configure the memory on die termination resistors' WR for channel B. ODT NOM (CHA) Use this to change ODT (CHA) Auto/Manual settings. The default is [Auto]. ODT NOM (CHB) Use this to change ODT (CHB) Auto/Manual settings. The default is [Auto]. Command Tri State Enable for DRAM power saving. MRC Fast Boot Enable Memory Fast Boot to skip DRAM memory training for booting faster. FIVR Configuration FIVR Switch Frequency Signature Select whether to boost or lower the FIVR Switch Frequency. FIVR Switch Frequency Offset Configure the percentage of frequency boost or deduction. CPU Override Voltage Configure the voltage added to the CPU when the system is under heavy load. CPU Voltage Offset Configure the dynamic CPU voltage added to the CPU. 61 English

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B85M-ITX
61
English
Configure IO latency for channel A.
IO-L (CHB)
Configure IO latency for channel B.
ODT WR (CHA)
Configure the memory on die termination resistors' WR for channel A.
ODT WR (CHB)
Configure the memory on die termination resistors' WR for channel B.
ODT NOM (CHA)
Use this to change ODT (CHA) Auto/Manual settings. °e default is [Auto].
ODT NOM (CHB)
Use this to change ODT (CHB) Auto/Manual settings. °e default is [Auto].
Command Tri State
Enable for DRAM power saving.
MRC Fast Boot
Enable Memory Fast Boot to skip DRAM memory training for booting faster.
FIVR Configuration
FIVR Switch Frequency Signature
Select whether to boost or lower the FIVR Switch Frequency.
FIVR Switch Frequency Offset
Configure the percentage of frequency boost or deduction.
CPU Override Voltage
Configure the voltage added to the CPU when the system is under heavy load.
CPU Voltage Offset
Configure the dynamic CPU voltage added to the CPU.