ASRock H510M/ac User Manual - Page 61

DRAM Timing Configuration

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DRAM Timing Configuration Load XMP Setting Load XMP settings to overclock the memory and perform beyond standard specifications. DRAM Reference Clock Select Auto for optimized settings. DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically. DRAM Gear Mode Gear2 mode doubled the ratio in memory controller, and it is good for high frequency. System Agent Geyserville Configure System Agent Geyserville (SA GV) settings. Primary Timing CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay and Row Precharge (tRCDtRP) RAS# to CAS# Delay : The number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge: The number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) The number of clock cycles required between a bank active command and issuing the precharge command. Command Rate (CR) The delay between when a memory chip is selected and when the first active command can be issued. 52 English

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52
English
DRAM Timing Configuration
Load XMP Setting
Load XMP settings to overclock the memory and perform beyond standard specifications.
DRAM Reference Clock
Select Auto for optimized settings.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted
and assign the appropriate frequency automatically.
DRAM Gear Mode
Gear2 mode doubled the ratio in memory controller, and it is good for high
frequency.
System Agent Geyserville
Configure System Agent Geyserville (SA GV) settings.
Primary Timing
CAS# Latency (tCL)
°e time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay and Row Precharge (tRCDtRP)
RAS# to CAS# Delay : °e number of clock cycles required between the opening of a row
of memory and accessing columns within it.
Row Precharge: °e number of clock cycles required between the issuing of the precharge
command and opening the next row.
RAS# Active Time (tRAS)
°e number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
°e delay between when a memory chip is selected and when the first active command can
be issued.