ASRock H81M-WW User Manual - Page 43

DRAM Reference Clock, DRAM Frequency, DRAM Tweaker, CAS# Latency tCL, in response.

Get ASRock H81M-WW PDF manuals and user guides View all ASRock H81M-WW manuals
Add to My Manuals
Save this manual to your list of manuals

Page 43 highlights

H81M-WW Load XMP settings to overclock the DDR3 memory and perform beyond standard speciications. DRAM Reference Clock Select Auto for optimized settings. DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically. DRAM Coniguration DRAM Tweaker Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to conirm and apply your new settings. CAS# Latency (tCL) he time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay (tRCD) he number of clock cycles required between the opening of a row of memory and accessing columns within it. 39 English

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
H81M-WW
39
English
Load XMP settings to overclock the DDR3 memory and perform beyond standard
speci±cations.
DRAM Reference Clock
Select Auto for optimized settings.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted
and assign the appropriate frequency automatically.
DRAM Con±guration
DRAM Tweaker
Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to con±rm
and apply your new settings.
CAS# Latency (tCL)
He time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay (tRCD)
He number of clock cycles required between the opening of a row of memory and
accessing columns within it.