ASRock H81M-WW User Manual - Page 45

tRDRD, tWRRD, Use this to change DRAM tRRSR Auto/Manual settings. He default is [Auto].

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Page 45 highlights

H81M-WW tCKE Conigure the period of time the DDR3 initiates a minimum of one refresh command internally once it enters Self-Refresh mode. tRDRD Conigure between module read to read delay. tRDRDDR Conigure between module read to read delay from diferent ranks. tRDRDDD Use this to change DRAM tRWSR Auto/Manual settings. he default is [Auto]. tWRRD Conigure between module write to read delay. tWRRDDR Conigure between module write to read delay from diferent ranks. tWRRDDD Use this to change DRAM tRRSR Auto/Manual settings. he default is [Auto]. Conigure between module write to read delay from diferent DIMMs. tWRWR Conigure between module write to write delay. tWRWRDR Conigure between module write to write delay from diferent ranks. tWRWRDD Conigure between module write to write delay from diferent DIMMs. tRDWR Conigure between module read to write delay. tRDWRDR Conigure between module read to write delay from diferent ranks. tRDWRDD Conigure between module read to write delay from diferent DIMMs. 41 English

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H81M-WW
41
English
tCKE
Con±gure the period of time the DDR3 initiates a minimum of one refresh
command internally once it enters Self-Refresh mode.
tRDRD
Con±gure between module read to read delay.
tRDRDDR
Con±gure between module read to read delay from diµerent ranks.
tRDRDDD
Use this to change DRAM tRWSR Auto/Manual settings. He default is [Auto].
tWRRD
Con±gure between module write to read delay.
tWRRDDR
Con±gure between module write to read delay from diµerent ranks.
tWRRDDD
Use this to change DRAM tRRSR Auto/Manual settings. He default is [Auto].
Con±gure between module write to read delay from diµerent DIMMs.
tWRWR
Con±gure between module write to write delay.
tWRWRDR
Con±gure between module write to write delay from diµerent ranks.
tWRWRDD
Con±gure between module write to write delay from diµerent DIMMs.
tRDWR
Con±gure between module read to write delay.
tRDWRDR
Con±gure between module read to write delay from diµerent ranks.
tRDWRDD
Con±gure between module read to write delay from diµerent DIMMs.