ASRock X299 Taichi User Manual - Page 70

CPU2/SRC1 Slew Rate, SATA Slew Rate

Page 70 highlights

CPU BCLK Amplitude Configure the BCLK Amplitude for ClockGen. SRC BCLK Amplitude Configure the BCLK Amplitude for SRC. SATA BCLK Amplitude Configure the BCLK Amplitude for SATA. CPU1 Slew Rate Configure the CPU Slew Rate. Adjust the BCLK signal by defining the maximum change rate of the output voltage. Higher value will result in a shorter signal rising time. CPU2/SRC1 Slew Rate Configure the CPU2/SRC1 Slew Rate. Adjust the BCLK signal by defining the maximum change rate of the output voltage. Higher value will result in a shorter signal rising time. SRCO Slew Rate Configure the SRCO Slew Rate. Adjust the BCLK signal by defining the maximum change rate of the output voltage. Higher value will result in a shorter signal rising time. SATA Slew Rate Configure the SRCO Slew Rate. Adjust the BCLK signal by defining the maximum change rate of the output voltage. Higher value will result in a shorter signal rising time. CPU PLL ORT Configure the CPU PLL ORT. Overshoot Reduction Technology improves the BCLK signal to decrease overshoot/undershoot. PCIE PLL ORT Configure the PCIE PLL ORT. Overshoot Reduction Technology improves the BCLK signal to decrease overshoot/undershoot. CPU Output Divider Configure the CPU output divider. 64 English

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English
64
CPU BCLK Amplitude
Configure the BCLK Amplitude for ClockGen.
SRC BCLK Amplitude
Configure the BCLK Amplitude for SRC.
SATA BCLK Amplitude
Configure the BCLK Amplitude for SATA.
CPU1 Slew Rate
Configure the CPU Slew Rate. Adjust the BCLK signal by defining the maximum
change rate of the output voltage. Higher value will result in a shorter signal rising
time.
CPU2/SRC1 Slew Rate
Configure the CPU2/SRC1 Slew Rate. Adjust the BCLK signal by defining the
maximum change rate of the output voltage. Higher value will result in a shorter
signal rising time.
SRCO Slew Rate
Configure the SRCO Slew Rate. Adjust the BCLK signal by defining the maximum
change rate of the output voltage. Higher value will result in a shorter signal rising
time.
SATA Slew Rate
Configure the SRCO Slew Rate. Adjust the BCLK signal by defining the maximum
change rate of the output voltage. Higher value will result in a shorter signal rising
time.
CPU PLL ORT
Configure the CPU PLL ORT. Overshoot Reduction Technology improves the
BCLK signal to decrease overshoot/undershoot.
PCIE PLL ORT
Configure the PCIE PLL ORT.
Overshoot Reduction Technology improves the
BCLK signal to decrease overshoot/undershoot.
CPU Output Divider
Configure the CPU output divider.