ASRock X670E Taichi Carrara Software/BIOS Setup Guide - Page 60
DRAM PDA Enumerate ID Programming Mode, DDR Training Options
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TSME Allows you to configure TSME setting. Configuration options: [Auto] [Disabled] [Enabled] Data Scramble Allows you to configure Data Scramble setting. Configuration options: [Auto] [Disabled] [Enabled] DDR Addressing Options Press [Enter] to configure DDR Addressing Options. Chipselect Interleaving Interleaves memory blocks across the DRAM chip selected for node 0. Configuration options: [Auto] [Disabled] Address Hash Bank Allows you to enable or disable bank address hashing. Configuration options: [Auto] [Disabled] [Enabled] Address Hash CS Allows you to enable or disable CS address hashing. Configuration options: [Auto] [Disabled] [Enabled] BankSwapMode Allows you to configure BankSwapMode. Configuration options: [Auto] [Disabled] [Swap APU] DDR Training Options Press [Enter] to configure DDR Training Options. DFE Read Training The item performs 2D Read Training with DFE on. Configuration options: [Auto] [Disabled] [Enabled] DRAM PDA Enumerate ID Programming Mode Allows you to configure DRAM PDA Enumerate ID Programming Mode. Configuration options: [Auto] [Sequential PDA enumeration mode] [Legacy PDA enumeration mode] DDR Memory MBIST Press [Enter] to configure DDR Memory MBIST. MBIST Enable Allows you to enable or disable Memory MBIST. Configuration options: [Auto] [Disabled] [Enabled] 56
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