ASRock Z390 Taichi Ultimate User Manual - Page 76

IO-L Offset CH

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Z390 Taichi Ultimate RTL Init Value Configure round trip latency init value for round trip latency training. IO-L Init Value Configure IO latency init value for IO latency training. RTL (CH A) Configure round trip latency for channel A. RTL (CH B) Configure round trip latency for channel B. IO-L (CH A) Configure IO latency for channel A. IO-L (CH B) Configure IO latency for channel B. IO-L Offset (CH A) Configure IO latency offset for channel A. IO-L Offset (CH B) Configure IO latency offset for channel B. RFR Delay (CH A) Configure RFR Delay for Channel A. RFR Delay (CH B) Configure RFR Delay for Channel B. ODT Setting ODT WR (A1) Configure the memory on die termination resistors' WR for channel A1. ODT WR (A2) Configure the memory on die termination resistors' WR for channel A2. ODT WR (B1) Configure the memory on die termination resistors' WR for channel B1. 69 English

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English
69
Z390 Taichi Ultimate
RTL Init Value
Configure round trip latency init value for round trip latency training.
IO-L Init Value
Configure IO latency init value for IO latency training.
RTL (CH A)
Configure round trip latency for channel A.
RTL (CH B)
Configure round trip latency for channel B.
IO-L (CH A)
Configure IO latency for channel A.
IO-L (CH B)
Configure IO latency for channel B.
IO-L Offset (CH A)
Configure IO latency offset for channel A.
IO-L Offset (CH B)
Configure IO latency offset for channel B.
RFR Delay (CH A)
Configure RFR Delay for Channel A.
RFR Delay (CH B)
Configure RFR Delay for Channel B.
ODT Setting
ODT WR (A1)
Configure the memory on die termination resistors' WR for channel A1.
ODT WR (A2)
Configure the memory on die termination resistors' WR for channel A2.
ODT WR (B1)
Configure the memory on die termination resistors' WR for channel B1.