ASRock Z490M Pro4 User Manual - Page 63

IOL Offset CH B

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IOL Init Value Configure IO latency init value for IO latency training. RTL (CH A) Configure round trip latency for channel A. RTL (CH B) Configure round trip latency for channel B. IOL (CH A) Configure IO latency for channel A. IOL (CH B) Configure IO latency for channel B. IOL Offset (CH A) Configure IO latency offset for channel A. IOL Offset (CH B) Configure IO latency offset for channel B. RFR Delay (CH A) Configure RFR Delay for Channel A. RFR Delay (CH B) Configure RFR Delay for Channel B. ODT Setting ODT WR (A1) Configure the memory on die termination resistors' WR for channel A1. ODT WR (A2) Configure the memory on die termination resistors' WR for channel A2. ODT WR (B1) Configure the memory on die termination resistors' WR for channel B1. ODT WR (B2) Configure the memory on die termination resistors' WR for channel B2. Z490M Pro4 57 English

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57
English
Z490M Pro4
IOL Init Value
Configure IO latency init value for IO latency training.
RTL (CH A)
Configure round trip latency for channel A.
RTL (CH B)
Configure round trip latency for channel B.
IOL (CH A)
Configure IO latency for channel A.
IOL (CH B)
Configure IO latency for channel B.
IOL Offset (CH A)
Configure IO latency offset for channel A.
IOL Offset (CH B)
Configure IO latency offset for channel B.
RFR Delay (CH A)
Configure RFR Delay for Channel A.
RFR Delay (CH B)
Configure RFR Delay for Channel B.
ODT Setting
ODT WR (A1)
Configure the memory on die termination resistors' WR for channel A1.
ODT WR (A2)
Configure the memory on die termination resistors' WR for channel A2.
ODT WR (B1)
Configure the memory on die termination resistors' WR for channel B1.
ODT WR (B2)
Configure the memory on die termination resistors' WR for channel B2.